Hi, there:
I am doing a design which only covers 10% of the slices...but after P&R, it spreaded all over the FPGA. How may I constrain it into, say, one corner...
How may I "nail down the logic into a known location"(Somebody told me this trick)?
BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't be used...
Kelvin