How many RAM words can I implement in my Xilinx FPGA?

Aha. I did the first thing you're supposed to do when you have a question like this-- Look at the datasheet (duh!).

It appears that there is more than enough block RAM inside the chip for what I would like to do.

Steve

Steve Battazzo wrote:

Look at the product guides for the Spartan 3(E)...

With the XC3S1000, you get 432kbits of Block RAM (384kbits usable in x16 configuration) and 120kbits of distributed RAM. To achieve 30Kx16, you need at least 480kbits - this practically means consuming the whole FPGA as a single RAM with nearly no room left for other functionality, assuming the extra logic needed to manage the distributed memory still fits. More likely than not, you will need to step up - the XC3S1200E would be the smallest S3 FPGA that could definitely fit this RAM with some room to spare.

Since large distributed memories have significant logic footprint (muxes, control signal fan-out, etc.) combined with either long access latencies (input + output pipelining) or slow performance (large non-pipelined muxes and decoders), you will have to look at the XC3S1500 or XC3S1600E if you need your memory to be fast and low-latency: these are the two smallest S3 devices that can implement your RAM entirely within Block RAMs.

Thanks for the answer, Daniel! That helps a lot. I pretty much have to work with what I have on this dev board, so unfortunately I can't consider switching to bigger S3 devices. Also, when I was doing this in my head I underestimated the amount of memory I'd need.. it's actually quite a bit higher, meaning even the bigger devices wouldn't do it with on-chip memory.

This is ok, I have an external 8Mx16 SRAM at my disposal, the minor issue being that it's single port. I was hoping to avoid having to devise an efficient way to read/write data with that RAM chip, but it looks like this is what I'll have to do anyway...

Thanks again!

Steve

Daniel S. wrote: