How many layers are normally needed for PCBs using low cost FPGAs ??
I've just been told by a supposed board layout expert that the 256 pin BGA version of a Cyclone EP1C6 would require an 8 layer board (apparently having the entire underside of the device covered by balls with no free space at the centre makes signal routing a big problem).
Is this really true ??
Andre wrote: : How many layers are normally needed for PCBs using low cost FPGAs ??
: I've just been told by a supposed board layout expert that the 256 pin : BGA version of a Cyclone EP1C6 would require an 8 layer board : (apparently having the entire underside of the device covered by balls : with no free space at the centre makes signal routing a big problem).
With 0.3 mm drills, 0.6 mm vias and 0.14 mm lines spaces, the FBGA256 should be routable with a ground plane on 4 layers...
More layers will give you supply layers while with four layers you have to route the supplies with what is left after the signal routing.
Bye
-- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
If you were using Xilinx I would point you here
John Adair Enterpoint Ltd.
This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.
At least 6 layers. And 8 isn't unreasonable.
-- Greg snipped-for-privacy@hotmail.com.invalid (Remove the '.invalid' twice to send Email)
A layout technique called "channel routing" can reduce the number of layers significantly.
Leon
-- Leon Heller, G1HSM Email: aqzf13@dsl.pipex.com My low-cost Philips LPC210x ARM development system: http://www.geocities.com/leon_heller/lpc2104.html
John Adair wrote: : If you were using Xilinx I would point you here :
The examples omit all decoupling capacitors in the layout...
-- Uwe Bonnes snipped-for-privacy@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
If you can sqeak by with 240 pins I've got a custom 4 layer board running Nios with SDRAM and USB 2.0 incredibly stable at 110-120 MHz.
Stack is Signal-GND-PWR-Signal. Made 10 with ground pours, 10 without. Both sets function the same. I have not compared the external signals on an analog scope, but the clocks look good, the logic analyzer looks good, and they all work without glitch.
If you go to CompUSA and buy a few highspeed PCI cards you'll see they're doing their magic with only 2 layers with ground pours.
I was originally told by the board expert the same 8-layer requirement on our design. I talked him down to 6 and then went with 4 based on a lot of reading, looking at examples, and applying common sense.
I say listen to experts, but beware the advice of people who make more money if your design is more complex.
IMO Ken
Hi Andre, You should be able to break a 256-ball 1mm BGA in 4 routing layers and perhaps even 2 or 3 routing layers depending on the pin usage and FPGA design pinout choice. The details depend on your exact board technology, such as trace width. These are the signal layers, not including VCC and Ground planes. You may have VCCIO be different from VCCINT so you would have to take that into account. Potentially you could have a split VCC plane to cover VCCIO and VCCINT to save a layer.
The center pins are VCCint power and ground so they should be connected directly to planes. Via breakouts should go out in four different directions opening a space shaped like a cross to place VCCint decoupling caps under the BGA pattern.
It's hard to give a fixed answer for all circumstances as it's very dependent on both the FPGA design and the board technology that is available.
Ken (above) has a good suggestion about the Q240 - actually the EP1C6 Q240 and the EP1C6 F256 both have 185 IOs, so you would not lose any IOs by going to the Q240. However the F256 does have the advantage of being much smaller, so you can choose between board cost and size. Another option to consider.
Sincerely, Greg Steinke Altera Corporation snipped-for-privacy@altera.com
Hi Greg,
I was thinking more in terms of SI rather than routing difficulty.
In that case let me share how we handled that on only two signal layers. (We did to a split PWR plane, BTW)
It was a challenge with all the pins and signals and we wound up using a routing service. The company does nothing but apply a full up SPECTRA auto-routing system as a service to others. They were so knowledgeable and helpful and the whole transaction was done by email and phone over a few days. The price was incredible and now we'll save much more than their fee every batch of boards due to the fewer number of layers.
I suspect their routing experience has a bit to do with the stability of our boards as well.
Email me privately if you'd like the contact info. (remove the 1's)
Ken
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I've got 30 spartan2s sat next to me now. I went for the TQ144 package. We soldered them on ourselves here, onto two layer boards.
BGA is of course a completely different issue, but if you're using 'low cost' FPGA's you'll probably find one with a more 'sensible' package (such as TQ144)!!
Andy
Andre wrote:
-- Andrew Greensted Department of Electronics Bio-Inspired Engineering University of York, UK Tel: +44(0)1904 432379 Mailto: ajg112@ohm.york.ac.uk Fax: +44(0)1904 433224 Web: www.bioinspired.com
Did you make it past emissions testing? At what rate do your signals change? How is signal integrety? Getting a few boards to work in the lab is not as tough as getting a design to work in production in different envirinments while meeting goverment regulations.
Hi William,
Our fastest signals on the board will probably be the 32 bit SDRAM at
100-120 MHz. Our ADC's are operating at 6 MSPS (10 bit samples). USB 2.0 is operating at 30 MHz. Nios will match SDRAM.I need to look at the signals on an analog scope, but the logic analyzer is showing very low jitter operation and the clocks (both input and PLL generated output) look very clean and stable on my digital scope. The boards are operating at 110 MHz for as many days as I care to let them, so I'm fairly confident.
If you stay tuned, I'm sure I'll have a fun emissions testing story in a month or two. NTI was great help with our first board 3 years ago. I'm sure they'll be a big help again. We've shipped the products to 40+ countries since then with the biggest problem being that we once had to fax the emissions report to a diligent customs official.
Believe you me, my intimate intimate life-force-draining familiarity with production realities and EMC/Safety regulations is why I'm drooling over this new board. Lower parts count and layer count is key. Anyone who understands joint probability can see why.
Ken
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Sounds like you already selected the layer count.
I'd recommend the following two books if you haven't already looked at them. They are both right on the money.
Reducing layers often results in voids on the plane layers which leads to impedance mismatches and cross talk. Using ADCs, as well as digital ICs that have VCCOs different than internal VCCs can lead to less than ideal use of plane islands. Add to this some application notes put out by vendors that give bad advice (when compared to the tried, true, and tested advice given in the above two books), and you can run into trouble. I.e., you should always follow application notes regarding layout recommendations. Some are on the money, others mis-apply rules of thumb.
Also watch for board designers that use via anti-pads that are so large on the plane layers that they result in copper voids (see above).
Finally, if you can, get a digital scope with a FET probe and use very low impedance grounds for the probes for lab validation of your simulations and calculations (final sanity check).
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