It seems that bufio has the lowest clock skew in order to clock the oserdes. OSERDES in my configuration requires two clocks 1x clk and 2x clock. I would like to know how many OSERDES can I drive using one BUFIO. I would like to bring in limited number of clocks inside the part and avoid using bufg has it has 270 ps of clock skew as opposed to 50 ps of clock skew for bufio.
Thanks.
OSERDES in my configuration requires two clocks 1x clk and 2x clock. I would like to know how many OSERDES can I drive using one BUFIO. I would like to bring in limited number of clocks inside the part and avoid using bufg has it has 270 ps of clock skew as opposed to 50 ps of clock skew for bufio.
It depends on a few things (bonded or bonded I/Os, bottom or top of the device, etc). In general, For V4, each BUFIO can reach 3 clock regions and each clock region has
32 I/Os. For V5, each BUFIO can only reach 1 clock region each clock region has 40 I/Os.You can use ADEPT
Cheers, Jim
Thanks Jim. I will read about the Adept software. I am trying to use about 100 oserdes in a source sunchronous application. The oserdes output is brought external to the V5 FPGA. But at this point I am trying to understand the factors that can introduce skew on the source synchronous output at the output pins of the FPGA.
Three factors come to mind are
(1) Clock skew - This can be mitigated by using bufio instead of bufg (2) Internal Trace routing mismatches from oserdes to the the pad - Don't know how to mitigate this one consistantly. (3) Internal routing mismatch from internal flip-chip pad to the fpga pin (?) - This can possibly mitigated by adjusting the board trace lengths.
Basically I am trying to minimize the skew. Any guidance along those lines will be great.
Thanks.
oserdes in a source sunchronous application. The oserdes output is brought external to the V5 FPGA. But at this point I am trying to understand the factors that can introduce skew on the source synchronous output at the output pins of the FPGA.
Internal Trace routing mismatches from oserdes to the the pad - Don't know how to mitigate this one consistantly. (3) Internal routing mismatch from internal flip-chip pad to the fpga pin (?) - This can possibly mitigated by adjusting the board trace lengths.
will be great.
Not sure what exactly you are trying to do. The BUFIO input can only come from a clock capable pin, so I don't know how you are going to forward a clock for your source synchronous application. Also the BUFIO can only reach max 40 IOs in V5. BUFIO is mainly for source synchronous data capture application.
Cheers, Jim
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