How many decoupling capacitors need on one device?

This, and more:

Aust> Hi, all.

If my memory isn't faulty have a look at Xilinx application note XAPP623 for a full treatment of this subject. Otherwise the Xpower tool usually gives some recommendations about sizes and numbers of. Usually it is very difficult to achieve the reccomended numbers even if you use capacitor arrays like we do in our products. Genarally a pyramid of values/size is recommended.

John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 Development Board.

There are many techniques for decoupline - here is a summary of the way I do it - I do not claim it is the best but it seems to work well for me :

1. Use planes for all power supplies (at least locally to the device)
2. Put the planes on adjacent inner layers (I use VCCINT-GND-VCC as a minium) - at the very fastest pulse current demands, the parallel plat capacitance of the planes is very important
3. Place a large low ESR high reliability bulk capacitor near to the device on each supply (I use 100uF Sanyo POSCAP) - connect these to the planes through multiple vias (not thermally relieved)
4. Place 100nF 0603 capacitors on as many supplies as possible, using the obvious GND-VCCINT-VCCIO pairs that the vendor where possible. At least make a complete ring around the device, and if it is a BGA device, fan out the balls so that a "+" shapes of capacitors can be created on the back of the board under the device
5. Place a few larger ceramics as close to the device as possible
6. Use at least two vias (more if possible) to the planes for each connection and do not thermally relieve these vias
7. Capacitors that connect to the device without going through a via are much more useful

Not very scientific, but I've decoupled >1GHz CPU's and >166MHz FPGA's this way without any problems.

Another thing to consider is what creates the impulse current demands that make decoupling so critical. In this regard, consider making your design use non-simultaneous output switching, and use slow dV/dt and low drive strength output options where you can.

Hope this helps

We use multilayer boards with a solid ground plane layer and, when possible, one additional plane for each supply. But we often split a plane between, say, VCCINT and VCCAUX to save layers, one supply pour "inside" the chip footprint and the other "outside". We generally use four 0805 or 0603 ceramic caps, 0.33 uF each usually, per supply per chip, 12 caps total for a typical FPGA. Works fine.

I've never done a multilayer board that had too few bypass caps. 12 per FPGA may be too many, for all I know. TDR testing and real-life noise measurement have convinced me that using huge numbers of caps, or mixing cap values, isn't beneficial.

John

The number and value of caps has a minimum, of course. Much depends on the speed you are running the device at and the current profile. If you have large pulsed currents (as you would if you implement a processor core and connect to external memory) you will need both more bulk bypass and high frequency bypass than if you are using (almost) constant current differential drivers for something.

Board layout is key, of course. As John notes, a good plane system works wonders (and works really well if you can have the ground and power planes adjacent).

So the answer is 'it depends on the power / speed / current profile for your implementation'.

Cheers

PeteS