Hi, I have a question about ADC input to FPGA. Although I read some past thread on ADC connection with ADC. I still don't understand how to downconvert Giga Hz adc in FPGA. The new ADC, for example ADC08D1500, can support 1.5GSPS or even more. Its manufacture gives the demo prototype which has Xilinx FPGA. To downconverter the ADC data, I think the FPGA digital filter must be upto 1.5GSPS. Then, low throught data can be obtained by decimation. The fastest multiplier in FPGA is DSP48(?). It can be as fast as GSPS now? Could you tell me what's the technique to downconvert GSPS data in FPGA? Thanks in advance.
- posted
16 years ago