How do I use the Xilinx USB download cable for testing?

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Fellow Designers,

I am looking for a more convenient way to use inexpensive eval boards to
test logic designs in an fpga. I do this quite a bit already by designing
stimulator logic to put in front of my design and watching the results in
ChipScope. This is a lot of extra "throw-away" logic to design and usually I
only hit a limited number of test cases.

What I  really want is a convenient way to interact with my design at run
time. What I have in mind is a small piece of logic that connects to the
JTAG TAP controller inside the FPGA and gives me a simple read-write bus to
read and write registers and memories inside the FPGA. Then I would need a
little application that runs on the PC to let me peek and poke addresses.
The application should also let me run batch files that would be a list of
reads and writes of addresses.

Has anyone heard of such a helper application like this exists for Xilinx
fpga's?

Does Xilinx provide details of their chips and cable drivers to allow
someone to develop such an application?

I know all this is possible because Chipscope itself is such an application.
However, as far as I know, ChipScope does not let the user write into the
chip to control a design.

Any comments welcome.

  Pete Dudley




Re: How do I use the Xilinx USB download cable for testing?

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Look at http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm

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They provide an API. Look in the manual of chipscope 9.1 , it's called "jtag
cse",
you can "pilot" the thing.

Note that the API has changed radically between 8.2 and 9.1, and the xcell
article may use the old one ... but there are some examples and with some tests
you can achieve what you want.

I personnaly like it because with just one BSCAN component, I can "pilot" debug
function in the FPGA easily ... and then remove it in the final bistream.


    Sylvain

Re: How do I use the Xilinx USB download cable for testing?

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It is possible to do this without a board or an FPGA.

Maybe I've logged too many hours debugging
logical problems at a lab bench. but
the novelty seems to have worn off.

I use modelsim, an RTL viewer and
static timing to verify FPGA logic designs.
I expect the design to just work on the bench.
If it doesn't, I fix the process.

  -- Mike Treseler

Re: How do I use the Xilinx USB download cable for testing?
Mike

I agree with you that an HDL simulator and a few testbenches should always
be the first line of attack.

My problem comes in when I have to run 100 million clock cycles to verify a
design. This often happens with DSP designs that require a lot of data
through the filters to verify their functionality. Another case is when the
data is a two dimensional array and the operation is something like a 2D
FFT. It's easy to hit cases where its impossible to simulate the whole
thing. Granted its usually possible to cut down a simulation by changing
count limits, etc.

In any case, I'm hoping that the USB interface might be easy to use though
it could also turn into a project of its own.

Also, in theory, I could hand over an eval board to software developer and
they could start programming. The USB download cable could stand-in for the
pci interface that will eventually be there.

Anyway, I just wanted to make it clear the special circumstances where I
would use hardware verification. Definitely, I will always use the simulator
to the maximum extent possible.

Thanks for the reply.

  Pete



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Re: How do I use the Xilinx USB download cable for testing?
Hi Pete-

For DSP applications, this is exactly what the hardware co-simulation engine
of  System Generator for DSP does.  Check out
http://www.xilinx.com/ise/optional_prod/system_generator.htm for more
details.

As Sylvain mentioned, you can build your own "HW co-sim" engine by attaching
logic to the BSCAN component and using the CseJTAG Tcl interface to
communicate with it using the USB-to-JTAG cable.  While it's not trivial, it
shouldn't be too much trouble to come up with a simple example to read and
write registers in your design via JTAG.  For details on attaching logic to
the BSCAN interface, refer to
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=krs_blockRAM&iLanguageID=1&iCountryID=1 .
For details on the CseJtag Tcl interface, check out chapter 5 of
http://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_9_1i_ug029.pdf
and/or download ChipScope Pro (free for 60-days) and try out the
"csejtag_example1.tcl" example that comes with the tool.

Cheers,

-Brad




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Re: How do I use the Xilinx USB download cable for testing?


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I've done this with some Altera parts. Added my own JTAG accessible
register which I've used to program an external microcontroller via
the FPGA. I created a SVF file to do the programming so I could use
mostly any JTAG programming software (e.g. Impact)

Petter

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Re: How do I use the Xilinx USB download cable for testing?
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Have you tried looking at ChipScope's VIO (Virtual Input/Output Core)?
It might be exactly what you need.

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