I used [31:0] to pass on the integer to my task, but it won't compare with "count" which is of integer type.
How can I solve this?
task mytask: input [31:0] my_int; integer count;
blah if (my_int == count) begin do_something end
end endtask
I used [31:0] to pass on the integer to my task, but it won't compare with "count" which is of integer type.
How can I solve this?
task mytask: input [31:0] my_int; integer count;
blah if (my_int == count) begin do_something end
end endtask
Got it
input integer my_int;
Dear Mr. Ken, I recommend you search for this on Google :- vhdl math tricks Mr. Jim has written a very enlightening article. Yours &c, Mr. Syms. p.s. You may also like to know that the usenet group comp.lang.vhdl is useful for the kind of question you posed.
tee hee, all you'll get there is chuckles - the OP's problem was a Verilog, not VHDL, problem; he was effectively trying to compare a reg[31:0] with an integer, and (I guess) being badly confused because Verilog does unsigned comparison if any unsigned operand appears in the expression - and all reg[] variables are unsigned unless you explicitly set them to be signed. In VHDL you don't normally have this kind of problem (unless you use goofy packages like std_logic_unsigned); things either do what you expect them to do, or give rise to a compiler error.
Try this in Verilog:
reg [7:0] Byte; ... Byte = -3; // legal, gives binary 11111101 if (Byte < 0) $display("Negative"); // nope, Byte is unsigned! else $display("Positive"); // this is what you get, Byte==253
The solution of passing an integer argument to the task is fine as long as you are happy for it to be an unspecified bit width (at least 32 bits, possibly more). If your tools support Verilog-2001 then it's also possible to pass a "reg signed [31:0]" into the task, and then you keep control over the bit width whilst still preserving signed arithmetic.
Caveat scriptor :-)
-- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how
Whoops, you're of course quite correct. (Must not post before 1st coffee of the day!) I just assumed it had to be VHDL because Verilog blithely parses whatever you feed it! Thanks for correcting that Jonathan, Syms.
[...]
no problem... language confusion seems to go with the territory in EDA-land. Swapping among Verilog, VHDL, SystemVerilog, Tcl, e, C, C++ and so on, the usual question is "where does the semicolon go TODAY?". The charitable excuse is that there are more languages to worry about these days; the real reason is that my memory ain't what it used to be!
-- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how
Thank you Symon & Jonathan. Your information are very useful.
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