How do I make dual-port RAM from single port RAM?

estimate your worst case data rates and take a ram with the sum of these data-rates (plus overhead) ...

then you need to build some logic to switch between Port A and B to transfer concurrent access to a sequential access scheme

bye, Michael

You might get a better idea of the particulars by looking at a data sheet for IDT dual-port memories.

For some applications 2 Srams can be used in an alternate buffer configuration. I assume your 2 ports have similar issue rates otherwise you may have to mux in time.

For dual read ports and a single write port, this is easy. You just use two RAMs and always write to both of them together, but read from them separately, with each treated as a separate read port. For dual write ports, it gets a lot harder.

Yeah, the original codes are designed with Xilinx DPRAM with a functional testbenches, now I need to convert the codes into ASIC implementation. The tougher part of it is, I have little understanding of the functionality of the design.

Yeah, there are RAMs in the ASIC library supporting dual read/single write. I need to make dual read/write out of it. How can I do it now?

Thanks.

As someone else suggested, you could time-multiplex the two ports, which will take a double-speed clock and extra logic for the multiplexing. And this assumes that you are treating this as a synchronous RAM.

And someone else suggested that you look at your application and see whether you really need a full dual-port RAM, or whether you are dealing with a special case where you can segregate it into independent parts.

You could build the memory from multiple smaller RAMs and add decode logic to allow you to do two writes, as long as the writes were to separate RAMs. If they weren't, one of them would have to wait until the next cycle. This requires that the other logic trying to do the write be able to wait if the memory was "busy". Note that real dual-port memories are effectively implemented this way, except that the RAM granularity is a single word in the memory. The designers of those have the advantage that they are designing all the decode logic, down to the word level.

You can reduce the chance of collisions in this scheme by choosing which address bits select a RAM and which ones select a word in the RAM, if you know something about the likely access patterns. For example, it may be more likely that two memory writes are going to the same half of the memory than that they are both going to even (or odd) addresses.

If you can't multiplex, and can't deal with collisions, then you are out of luck. If you want to use predefined RAMs with their predefined single-port decoding logic, then you are stuck. Getting true dual-port requires specialized decode logic in the RAM.

Sounds like a powerful FPGA argument: Ifyou really need a true dual-port memory (read and write from either or both ports simultaneously), you are out-of-luck in the ASIC world, but you can do this just fine in FPGAs. Nice to know we have such an edge... Peter Alfke, Xilinx

"Frank @ CN" skrev i meddelandet news:du1a67$9g1$ snipped-for-privacy@reader01.singnet.com.sg...

You can instantiate FOUR rams and implement a valid bit for each location in a register. PortA can write to RAM0,RAM1 and read from RAM0 and RAM2 PortB can write to RAM2,RAM3 and read from RAM1 and RAM3

When PortA writes to address position 17, both RAM0[17] and RAM1[17] are updated and the VALID_BIT[17] is set to 0 indicating that RAM0,1 are valid instead of RAM2,3.

When PortB reads address position 17, both RAM1 and RAM3 are read. A multiplexer on the output is controlled by the selected VALID_BIT, and since VALID_BIT[17] is zero, it will select the output of RAM1 over RAM3.

Obviously this is going to use some gates,so it is not practical for large SRAMs. Running the RAM at 2 x frequency is going to cost a lot less.

--
Best Regards,
Ulf Samuelsson
This is intended to be my personal opinion which may,
or may bot be shared by my employer Atmel Nordic AB

So if you are back porting from FPGA to ASIC something stands out right away which makes this even more messy. Your logic & wiring paths will now gain significantly in performance but a comparable DPRAM is similar in performance between ASIC and FPGA for same feature and memory sizes since they are the same thing (almost). Perhaps there is an option to double up processing on the logic side rather than try to double up on SPRAM side.

At this point I can only suggest before continuing with the ASIC, redo the FPGA design so that it also only uses 1 port atleast you don't burn masks, tie your hand behind your back on the cheap. Then it should be easier to convert, atleast you can prove the redesign before conversion.

Your other option if you really really must use 2 concurrent writes with no other possibility is to go and get a DP WW RAM core from one of the ASIC IP houses, Mentor, Cadence, Synopsys and a couple of others come to mind, not sure who has which. I thought most of the asian foundries would include such blocks in their library, otherwise it seems you have a limited library.

So what is the application, & size of DP WW RAM ?

John

The reason I ask for DP WW size is that for applications in say DSP and data buffering, the memory size might be large but there are possible options in architecture.

In say a cpu datapath design with a N way ported register file the options may be far fewer but the size may be much smaller and ameniable to brute force as suggested by the 4 way Ulf design. That probably requires that a DP WW store stiil needs to be built but only for 1 bit direction flag and to the granularity of words or super words if I understand it right.

John

I just converted a quad port 2r2w to F/Fs this morning; luckily, it was easy to simplify. You don't give enough info - are the clocks related? How big is it? Do you have higher frequency clocks available?

Curious that you should have a library with no 2rw memories in it. Can you tell us whose it is? It sounds like it may too new to be usable.

Sean

I've been trying to follow your problem and now have time to lend some help. I'm going to approach this from a black-box design point of view.

First question is how are in implementing it or what language are you using (VHDL, Verilog or something else)?

What size device are you looking to create (data and address bus width)? Or are you trying to create a library device?

What device and signals in the original design being used?

Derek

Presumably this depends on what ASIC libraries you have. There is no inherent reason that an ASIC library could not include dual-port memories. Apparently the original poster's didn't.

That is a clever solution that I hadn't thought of. Of course, your VALID_BIT array needs the capabilities of a true dual-port memory. So this doesn't really build a dual-port memory just out of RAMs. It builds it from 4 RAMs and a smaller dual-port memory (just as many elements, but only 1 bit wide). You would have to build that smaller dual-port memory out of flip-flops. The result still might be smaller than building the full-size memory out of flip-flops.

True, some TSMC ASIC libraries had dual-read/write memories, and they used to provide memory generators which enables creating the memory blocks of any capacity.

After we changed foundry, things got really complicated. In the new library, only a few memories are provided and the width & depth are also fixed. It becomes very inefficient to use these RAMs.

I guess I am out of luck on memory issues this time.

Morning Samuelsson & sharp, I haven't got time to study the sequence of the clever solution yet. I want to know is, does it have the function of a full dual port R/W RAM if the R/W accesses of both ports are random? My RAM is 130*6bit, and the IP uses eight pieces of this RAM.

TIA

Yes, Ulf's solution gives full dual-port functionality for arbitrary addresses (though of course you have to decide which port gets the last word in case of simultaneous writes to the same address, as with any dual-port memory).

But with your small word size of 6 bits, this may not be cost-effective. The VALID_BIT array requires similar logic to a

1-bit-wide dual-port memory (not quite the same, since port 0 always writes a value of 0 and port 1 always writes a value of 1). So you have to design something close to a 130*1bit dual-port memory out of flip-flops and logic, and use that with four 130*6bit RAMs (or two 130*6bit dual-read/single-write RAMs, since you indicated you have those). You might be as well off to design a 130*6bit dual-port memory from flip-flops and logic.