1. Home
  2. Field-Programmable Gate Arrays
  3. How do I fix this type of errors?

How do I fix this type of errors?

Hi, there:

I am performing partial reconfiguration tutorial. How do I fix this error in the final assembly stage?

Thanks for your advice. Kelvin

Starting Guide File Processing.

Loading device database for application Par from file "../../pims/iq_gen/iq_gen.ncd". "sig_gen" is an NCD, version 2.38, device xc2v250, package fg256, speed -4 The STEPPING level for this design is 1. FATAL_ERROR:Guide:basgitaskphyspr.c:255:1.28.20.2:137 - Guide encountered a Logic0 or Logic1 signal GLOBAL_LOGIC1_32 that does not have a driver or load within the module boundary. This problem may be caused by having a constant driving the input from outside the module boundary or because a driver or load comp did not meet the par-guiding criteria. The design will not be completely placed and routed by Par-Guide Process will terminate. To resolve this error, please consult the Answers Database and other online resources at

formatting link
If you need further assistance, please open a Webcase by clicking on the "WebCase" link at
formatting link

Reply to
kelvin8157
Loading thread data ...

Hi Kelvin, try checking all your constant signals. especially the ones connected to your bus macros and clock buffer(s).

greets simon

Reply to
user

Hi Kelvin,

did you ever get that problem fixed, or find out something new about it?

I get the same error, and the strange thing is that the signal is definitely WITHIN module boundaries when I look at the corresponding .NCD. Plus, I'm using some generated cores inside this module and hence have no way of changing anything about any of the GLOBAL_LOGIC-signals...

Reply to
Sean Durkin

Sean:

I saw Kamal Patel sent a message to our inbox.

I couldn't get a definitive explanation for that error. I coded many varieties and flavors for my design, finally some of the pool passed without this error (& other errors), however I am not sure whether constants caused this error.

I found that at the final assembly stage, when I removed the "Closed" constraint in the Place & Route on the fixed module. And then my design ran without errors. My design was so complicated and had many many top level clock buffers and DCMs...Though I am not sure whether this trick work until the testing is out...

Best Regards, Kelvin

error in

encountered a

Reply to
kelvin8157

Which "closed" constraint do you mean? The "MODE = RECONFIG"-constraint? If I remove that, the design flow finishes without a problem, but of course the result is unusable, since lots of nets from the fixed module cross the module boundary to the reconfigurable module.

--
Sean Durkin
Fraunhofer Institute for Integrated Circuits (IIS)
Am Wolfsmantel 33, 91058 Erlangen, Germany
http://www.iis.fraunhofer.de

mailto:23@iis.42.de
([23 , 42]  [durkinsn , fraunhofer])
Reply to
Sean Durkin

Sean:

I removed the MODE, PLACE and GROUP on the fixed module only. My fixed module cover 80% of the whole chip. The reconfigurable module still has these "closed" constraints, but they cover only 20% on the left side of the chip... I haven't tested them in hardware yet.

#AREA_GROUP "FIXEDMODULE" MODE= RECONFIG; #AREA_GROUP "FIXEDMODULE" PLACE=CLOSED; #AREA_GROUP "FIXEDMODULE" GROUP=CLOSED;

Hope this helps...

Kelvin

Reply to
kelvin8157

Sean and Kelvin, I had the same problem (Fatal Errors due to logic0/logic1 on signals). The logic0/logic1 doesn't seem the problem itself but it leads in the right direction. In my case, the error was mostly caused by unconstraint top level logic.If the logic was moved into a module, the final par was successful. However, I still have trouble setting constant '0' and '1' on the bus macro inputs, which also causes your problem even if no real logic is involved. What puzzles me is that it works for the tutorial (xapp290). Please correct me if I am wrong. Markus

Reply to
Markus

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.