How do I fix this error?

I am using NCVerilog and Virtex2-6000. I tied RST pin of the DCM1 to 1'b0 in RTL code. RTL simulation was all right, but gate level simulation failed after at first rising clock edge.

SST2 Database Write API -- DWAPI Version 05.10-s016 -- 09/15/2004 Copyright 1997-2003 Cadence Design Systems, Inc.

Timing Violation Error : RST on instance sim_sincos.i_sincos.DCM1 must be asserted for 3 CLKIN clock cycles.

Warning! Timing violation $setuphold( posedge I0:675 PS, negedge S:136 PS, 553 :

553 PS, 0 : 0 FS ); File: /home/qijun/projects/wlan_test/sincos/fpga/sincos.v, line = 1465 Scope: sim_sincos.i_sincos.buf_80m_n Time: 675 PS
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Sea Squid
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