How can we fully utilize available BRAMs...

Hi guys, I have a problem with how EDK utilizes BRAMs for data and instruction LMB memories. I have 64KB instruction and data space and I have 32 BRAMs on my chip. So basically I should have 32 * 18KB memory on my board. However when EDK wants to map the data and instruction memories on the BRAMs it really under-utilizes the BRAMs. It assigns 2KB (every bit of the word) of instruction and data on the either port of each BRAM. I've tried with different memory sizes and still it uses just 2KB on each port for data and instruction. I should be able to virually use

512KB of on chip memory but practically I can't use more than 128KB of my on-chip memory space. Do you know any way to change the way that EDK assigns words to the BRAMs?

Thanks beforehand,

Reply to
Xesium
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Do you have bytes or do you have bits? The BlockRAMs are 18 kbit (double for Virtex-5, 1/4 for Virtex/-E, Spartan-2/E).

Reply to
John_H

It's interesting. I have bytes. Actually when using Base System Builder I use 64KB (I hope Xilinx by B means bytes) of instruction and data LMB. My instruction and data address space is from 0000 to ffff. Considering that it's harvard architecture I assume that I have

64KBytes of instruction and data which use the two different ports of the BRAMs. It's a little bit confusing to me. Because I checked my system_init.vhd file and it seems that I have 16 Kbits (2KBytes) of memory on each BRAM. I used to think that it assigns each 2KBytes of my instructions and data (overall it becomes 4KB) to each BRAM. That exceeds the amount of memory on each BRAM. By the way what happens to the remaining 2Kbits if each BRAM has 18Kbits space?
Reply to
Xesium

Xesium schrieb:

the 'parity bits' are never used in the EDK BRAM blocks, so those are effectivly "vasted".

Antti

Reply to
Antti

Hi Xesium,

If you use BSB to generate your design, the default setting is actually not a Harvard architecture system. So no extra 2KB. :)

If you need Harvard architecture, from my experience, you need add a separate BRAM controller and BRAMs.

Wayne

Reply to
quickwayne

Hi Wayne,

so you mean that the address space that it shows which is from 0000 to ffff is the address space for both instruction and data? So how is it ordered? how does it distinguish between data and instruction? Because I think the compiler doesn't really consider it (At least I think)? And also I have this problem that I want to profile my application when it is executed on Microblaze but I don't know which address to set as profiling_mem. Can I assign or should I assign an address beyond the address space for data and instruction?

Thanks,

Reply to
Xesium

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