how can I use a signal defined in one Architecture to another Architecture

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Hello everybody,

I want to use the signal defined in one architecture in VHDL to
another architecture. I have two architecture in the same .vhd file
and I am using Component mapping. I required the result of calculation
of a signal to be used in second architecture. Can any one tell how to
defined signal so that it is globally visible to other architectures.

Regards

Khan

Re: how can I use a signal defined in one Architecture to another Architecture
 
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Hello Muhammad,

this is a common question.

The clean way for handling this is to feed the signal through
the port maps.

Regards,
Mario

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Digital Force / Mario Trams       snipped-for-privacy@informatik.tu-chemnitz.de
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Re: how can I use a signal defined in one Architecture to another Architecture
Hi Khan,
  If you declare a signal in a package and you include the package
then the signal can be globally used by all architectures that
reference that package.   This is for simulation only and will not
work for synthesis.

Jon


snipped-for-privacy@hotmail.com (Muhammad Khan) wrote in message
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Re: how can I use a signal defined in one Architecture to another Architecture



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This will work for synthesis in Synplify Pro 7.3.


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