Hi, all ,
I am using ISE6.2 and modelsim5.8b. My design is composed of two modules, one is VDHL design ,and the other is verilog design. Now I want to combine them together in a top level file (in vhdl) and simulate the whole design. Can I just instantiate the verilog design module with a compoenent in the top file and write a testbench for the top file. I have done this , but it fails when binding the verilog module (rx_backend). # ** Failure: Default binding had errors for entity 'rx_backend' on the component declaration of line 220. See the compiler messages. Could u give any idea on how to do the mixed vhdl and verilog design and simulation? Many thanks.
Jimmy