Hi, I am doing a large_scale design with Xilinx Virtex2 and at the end of it. Now,the modification of the design seems to be painful,for a bit modification will take a very long P&R. So I hope that there can be some suggestions about how to lock the unchanged portion of the design. Best rgds. Wosiqiu.
Look into modular or incremental design. The bad news is that you will have to take your design apart in order to comply with the constraints imposed by these approaches.
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian
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