How can I have multiple drivers of one inout port?

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Hi,

I am trying to connect the bidirectional ports of two components to
one bidirectional set of pins on my FPGA. Is it possible to do this in
VHDL? The following example does not appear to read the bidir port:

entity whatever
 port (
  signal choice   : in    std_logic;
  signal my_bidir : inout std_logic
 );
end;

architecture rtl of whatever is

signal x0_bidir,
       x1_bidir  : std_logic;

begin

 xInstOne : x
  port map (
    my_bidir_port => x0_bidir );

 xInstTwo: x
  port map (
    my_bidir_port => x1_bidir );

 my_bidir <= x0_bidir when choice='0' else x1_bidir;

end;

==========================

Is there any way to modify this to make it work, or am I stuck with
exporting both input and output ports from the components and muxing
them at the top level?

Re: How can I have multiple drivers of one inout port?
f'up comp.lang.vhdl set


Quoted text here. Click to load it

Take tri-state drivers

process(enable,some_signal)
begin
if (enable='1') then
    target_signal<=some_signal;
else    target_signal<=(others=>'Z');
end if;
end process;

target_signal has to be of std_logic(_vector), because it has to be
resoled (multiple drivers).

Take care, that *only one* of these tri-state-drivers are activated at a
time.

Take care, that everytime *at least one* driver is active (otherwise
target_signal would float).


Think about providing these enable-signals to the tri-state-drivers.
E.g. if you have several memory blocks, the address may decide, which
block is allowed to drive target_signal -> the enable-signals can be
generated thorugh combinational logic out of the address.


Ralf


Site Timeline