How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?

I know the simple answer will be use NisoII... But in my situation is ..I cannot use NisoII or any other soft/hard core processor (actually is..I am not able to use any asm/c ..whatever computer programing language).

I would want to know anyone try to build a FSM to "talk" with the Avalon bus before? What should I do/understand first for build a FSM to work as Master in Avalon bus?

My project require to receive packet and put them into memory and then I have another logic to read from the memory.

The data flow is that Ethernet --> PHY(chip) --> TSE MAC IP --> Avalon bus --> memory --

DDR2 controller ->DDR2 memory.

What I have now:

  1. PCI Express Development Kit, Stratix II GX Edition
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  2. DDR2 controller demo (non Avalon Bus), (it is work on the PCI Express Development Kit)
  3. TSE MAC IP (I did not try it..because all the demo are using NiosII)
Reply to
Yui
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The Avalon bus is exceptionally well documented. It is so easy to build masters and slaves for that bus that even I can do it.

But (IMHO) the only reason to use Avalon is to take advantage of NIOS. I would use Wishbone for the situation you describe.

The Wishbone bus is also very well documented.

Reply to
ghelbig

I disagree. Avalon is far better for high performance transfers, including first class support for split transaction and burst transfers. In it's native form, Wishbone can only transfer data every other cycle (due to the way handshaking , and the proposed support for streaming is a 2nd class citizen and I haven't seen it used anywhere.

Avalon works so well that I use it even outside the realm of NIOS II and without the support of of the SOC builder (I essentially have to replicate this functionality by hand).

Sustained Gigabit ethernet traffic will require a 32-bit bus running at 32+ MHz with Avalon. That should not be a problem.

Tommy

Reply to
Tommy Thorn

Yes, many times.

The Avalon specification would be the a good start.

While Wishbond and Avalon are both well documented, I would disagree with you about only using Avalon to take advantage of Nios. Tommy Thorn's post is right on the money about the ways that Avalon can be superior to Wishbone and I'd also add that for simple transactions with no read latency, Wishbone and Avalon are pretty much functionally identical, only the signal names are different. You don't need Nios, SOPC Builder or even be targetting an Altera part to make Avalon compatible widgets....but based on the questions of the original post, I think there are very basic hurdles that Yui needs to clear first since it doesn't appear that he has perused the Avalon specification since transactions are almost painfully simple handshakes (as with Wishbone).

Kevin Jennings

Reply to
KJ

Anywhere I can find some same for the "FSM" master in Avalon bus?

Reply to
Aiken

text -

You're going to have a hard time if you're not willing to pick up and read and attempt to understand the Avalon bus. If you have read it and are still asking about how to find a "FSM" master then it's apparent that you do not understand it so I would suggest some further study on your part.

In any case, no state machine is required, see below for the template that is Avalon compliant and insert your code where mentioned.

process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Read

Reply to
KJ

quoted text -

Spot on!

Tommy

Reply to
Tommy Thorn

Kevin,

I just looked at your template again. I think it's slightly wrong:

The "if (Read = '1') then" should be outside the dependency on waitrequest. The waitrequest only has bearing on the input, not on the output. It especially shows up with the slave supports multiple outstanding requests.

Regards, Tommy

Reply to
Tommy Thorn

The template is correct for an Avalon master that is not 'latency aware', which is a master that does not happen to support the optional 'readdatavalid' input. For a master that does support latency you would have the following code outside of the entire above loop which is what I think you're referring to.

if rising_edge(Clock) then if (readdatavalid = '1') then Data_That_I_Read

Reply to
KJ

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