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How can I get an output clock phased align with the input clock.

Hi,

I have several FPGAs in my design and I want the first FPGA to feed the other FPGAs with its master clock. The first FPGA use a DCM to reshape an input clock and get its master clock. I want the three FPGAs to have a phase-aligned clock. I just don't know how to do it since the master clock of the first FPGA which is the output clk0 of the DCM has to go through an output buffer to access a pin to be distributed to the others FPGAs but then the clock would have a delay compare to clk0. Is someone can help me with that ?

Thanks. Christophe.

Reply to
chris
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Hi Chris,

Basically you need a c>Hi,

Reply to
Luc Braeckman

snipped-for-privacy@hotmail.com (chris) wrote in news:33923a80.0406020327.20fde6f3 @posting.google.com:

Can't you just use two DCMs as shown in the FPGA datasheet to remove the skew caused by the buffer and PCB delays?

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Reply to
Dave Vanden Bout

Take a look at Xilinx App Note 174 - Figure 11 (Board Level Deskew of Board Level Clock between Multiple FPGAs.

The jist is that after your master FPGA generates its output clock at the PWB level, the signal is routed back into the FPGA BUFG input and is used to drive the FB input of the originating DLL/DCM. This is parallel for the Master FPGA as well as slaves.

Traces should be matched at the board level. Also, make sure you think about the reset philosophy of the multiple FPGAs on the board. This usually requires a little thought, since resets and clock availability are tightly coupled in synchronous design. Usually, the master FPGA also distributes a "reset" signal to apply to slave DLLs.

-- Regards, John Retta Owner and Designer Retta Technical Consulting Inc.

Colorado based Xilinx Design consultant

email : snipped-for-privacy@rtc-inc.com web :

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Reply to
John Retta

Hi Luc,

The master clock frequency is around 100MHz and is coming from an ADC.

Christophe.

Reply to
chris

Chris,

Do you need other frequencies in your FPGAs derived from this clock? Is it single ended or differential? What skew do you need to anticipate?

PLease let me know,

Luc

Reply to
Luc Braeckman

Hi Christophe,

Look on the Lattice website. They have released the part that I mentioned before. Look under clock management. Very easy interface, a lot of features, flexible profile management, etc.

Best regards,

Luc

Reply to
Luc Braeckman

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