How can I deal with the output signal in testbech?

hello: I have a small count design, which I want to do functional simlation in modelsim. the code are following; module count4(cnt,clk) output [3:0] cnt; input clk; reg [3:0] cnt;

always@(posedge clk) cnt = cnt +1; endmodule

This is just a 4 bits simple counter design. and I do not have the reset signal in it.(just for test). you see that the modelsim treat "cnt" as x at initial time, so the result can not be right. So I want to modify the cnt signal in testbench, I done as follows:

initial force cnt = 0; #500 release cnt;

and the clk is 100. but the reesult is not right either. My question is : How can I make the cnt to be a specific value in testbench? just not using the reset or preset, thanks.

Reply to
Devlin
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This problem have been solved

I should force the signal in the module level. just like this "force uut.cnt", uut this the instance of design moduel.

thank Srinivasan Venkataramanan

Reply to
Devlin

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