Hi all,
I want to add two 6 bits signed digit. Something like 6'b10_0110, the MSB '1' is negative digit,other'00100' is absolute value. Or Something like 6'b00_0110, the MSB '0' is positive digit,other'00100' is absolute value.
How to design a signed adder to add these too signed digit? Now I convert it to 2's complement,add, and convert it to signed digit. But the overflow control seems not be a easy task. BTW, I use verilog.
Any suggestions will be appreciated! Best regards, Davy
******************************************************************************** Davy, If the data is in 2's complement then just add the two numbers together and you will get the right answer. Remember, 2's complement addition is the same as straight binary. As far as the over flow is concerned, if the sum is not going to exceed the max possible result defined by your resolution(#of bits) you should be fine. Otherwise, just increase the width of the result to compensate for greater result. for example (-7)+(-7) in decimal is (101) + (101) in 2's complement the result (if you do not compensate the result by adding a bit is = (010) => +2 (WRONG!) whereas by adding a bit to the result will take care of this problem 101 +101
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1010 ->(-14) decimal (CORRECT!) Hope this helps.-MORPHEUS
Did you try 6'sb100110 + 6'sb000110 ? That is a signed addition. That is a lot safer than doing the 2's complement conversion your self and using '95 unsigned addition.
It is Verilog 2000, so use the Verilog 2000 mode on your tool (complain if they still don't support Verilog 2000).
Hi,
Thank you for your help!
But where can I get Verilog2001's tutorial or definition on this subject.
Thanks! Davy
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