Holding in output registers

Hi,

does QuartusII version 5.0 SP1 implement a holding function in output registers ?

If it does not, how can I solve the following example if I want to place "ls_data_out" in output registers ?

... ARCHITECTURE example OF XY IS

BEGIN

Data_out

There's no need for the "if no condition keep the value" assignment. The semantics of the clocked process that creates a flip-flop means that it's redundant.

"condition='1'" synthesizes to a clock enable whose effect is to gate the rising edge of the clock. (Of course on an FPGA, the clock enable is really a mux select -- look up "recirculating mux").

-a

Hi Andy,

your answer does not really answer my question. Independently of whether I use the redudant assignment in my VHDL or not

the holding of the D-flip flop is the problem. Is it possible to fit it into an output register ?

Rgds Andr=E9

The problem is not with Quartus but with the component you will use, of which you don't tell us anything.

Nicolas

Nicolas Matringe schrieb:

CycloneI EP1C12

Hello Andre,

Cyclone has clock enable on the I/O registers. You can see it in Fig

2-32 of the data sheet, as well as references to it in figure 2-30 & 2-31, and the description is between figures 2-31 & 2-32.

Hope this helps, Subroto Datta Altera Corp.

Hi Subroto,

thank you for the link.

Does that mean that the OE Register holds its value if clock enable is inactive ?

If so, is the clock enable "generated" automatically by Quartus when using the VHDL description above? Or do I have to instantiate an output register which includes clock enable as input port?

Rgds Andr=E9

Could it even make sense to describe the clock enable on my own and NOT to let the fitter recognize it automatically ? Could that have some performance advantages ?

Rgds Andr=E9