Hold violation in Virtex 4

Hi everyone:

I'm new to FPGA design (have always worked with ASIC before.) I'm working with Virtex 4, and from time to time, I'd get hold violations on one of my clocks, which XST cannot fix. This clock is driven with an IBUFG. I don't know how to work around this problem other than inserting delays with gates myself. I'd appreciate any feedback/idea on this problem.

Thank you,

-TT

Hi everyone:

I'm new to FPGA design (have always worked with ASIC before.) I'm working with Virtex 4, and from time to time, I'd get hold violations on one of my clocks, which XST cannot fix. This clock is driven with an IBUFG. I don't know how to work around this problem other than inserting delays with gates myself. I'd appreciate any feedback/idea on this problem.

Thank you,

-TT

The IBUFG is essentially the clock input pin buffer. The IBUFG is not intended to drive the fabric. The low-skew global clock net are driven by BUFGs (aka,BUFGMUX). So, typically you connect the IBUFG output to the BUFG input. I don't think you can get hold violations if the fabric is clocked by a BUFG.

Another typical connection is if you use a DCM (for phase deskew, phase shifting, clock multiplication/division, etc...). Then, the IBUFG drives a DCM input, a DCM output will then drive a BUFG input, and the BUFG output will also be routed back to the DCM feedback input (and, of course drive the fabric clock inputs).

Bob

Also, in V4 there are "local" clocking options. The pins labeled "CC" also have this thng called a BUFIO (local clock buffer). BUFIOs can drive IOB clock resources. BUFIOs can also drive BUFRs. BUFRs can drive (some of) the fabric (as do BUFGs).

It helps to have your own local dedicated FAE. Otherwise, you need to RTFM. I hate reading the f'ing manuals, so I have our FAE's phone number memorized. He has to answer our questions or we'll think bad thoughts about him, and if you're a Twilight Zone fan then you'll understand the ramifications of this.

Bob