High speed counters on Xilinx CoolRunner-II

Hi Bob,

It's not difficult at all to create a 40-input AND gate when targetting CoolRunner-II CPLDs.

Simply create an equation in VHDL that goes something like:

AND_GATE = input1 and input2 and input3 ... and input40;

There is one additional step you do need to do - And that is, make sure that the software implementation property for "Collapsing Input Limit" is changed from 32 (default) to 40. (With a default setting of 32, you will be limited to a 32 input AND gate)

Hope that helps! Mark

Robert S. Grimes wrote:

Hello again,

I need a 32 bit or so counter, clocked as fast as possible. Last week, Mark Ng (thanks again!) sent me a very simple counter that can be clocked > 400 MHz. Here is the code:

-- start Mark's code entity count32m is Port (clk : in std_logic; reset : in std_logic; MSB_Out : out std_logic); end count32m;

architecture Behavioral of count32m is

signal counter : std_logic_vector(31 downto 0);

begin process(clk, reset) begin if(reset = '0') then counter '0'); elsif (clk'event and clk = '1') then counter

(snip of fast counter code)

Does the timing analysis know you will only read it when it is not enabled? I would guess it is setup time to the latch reading the count. Static timing analysis probably assumes it could be counting.

-- glen

Yeah, that's sounds right, Glen; it's what I'm assuming. The problem is that I don't know how to tell it otherwise! I've done fairly complex designs before, but I've never had to deal with high speed. This project is fairly simple, but needs to high speed counters to measure the arrival times of pulses on two signals. So, I have three signals that enter via pins (counter clock and the two pulse trains of interest); the rest of the design can be relatively slower, maybe as much as three orders of magnitude.

I have found the Xilinx tools really easy to learn and use, but to really gain highest performance, they're not so simple...

Just looking for some pointers...

Thanks!

-Bob

There was a question here not so long ago about the meaning of static timing analysis. For a synchronous design the tools can compute the time it takes from the output of any FF, through logic to the input of any other FF. That time, plus the setup time of the FF determines the maximum clock rate. It is done without knowing which FF's are enabled on any clock cycle, and so might be overly restrictive.

It might be that you can tell the tools what you really mean, or you might just have to ignore the results of that analysis. The frequency you came up with is the frequency if you don't stop the counter.

-- glen

Do you real need binary counter in your application?

If you are searching to speed your design, try a LSFR architecture of your counter -> you will use more Flip-Flops but you will increase the speed !

Regards Laurent

Not true. An LFSR counter uses the same number of flip-flops as a binary or a Gray counter (if we disregard the fact that LFSR normally excludes one state). The trouble with LFSR is that any math is impossible in that code, but it is very easy to reverse the direction of count. BTW, the fastest counter is always a binary ripple counter, where the frequency resolution is determined by only one flip-flop's toggle rate. But you have to wait a while to read out data, after disabling the count. I remember that the original posting promised to do that. Peter Alfke ================