Hello everybody, I would like to implement a multiplier with word size equal to 16. However I read some book, for example "Computer Arithmetic" by Parhami, and I found only high radix multiplier radix-8 and radix-16 at maximum. Is there that can suggest me some good reference (book, articles etc) about this topic? Thanks a lot Giovanni
Presumably, if you post this to the arch.Fpga group, you mean to use an FPGA of some kind.
SpartanIII FPGA's (amongst others) from Xilinx provide very efficient embedded 18 X 18 multipliers.
Radix and word size are two different things.
Radix describes the unit operation that the larger multiplier is made out of. A higher radix allows a faster multiplier using more logic.
-- glen
Sorry, I mispelled. However I don't understand very well your mail: so you propose to use a high radix multiplier (something like a multiplier 3bit x 3bit) to create a large word multiplier (16 x 16)? If yes is there some hint that you can provide me about how to accomplish this task, how to put together the basic blocks? Thanks a lot, Giovanni
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