Have you considered Spinal ? It is a high level HDL based on Scala.
Have you considered Spinal ? It is a high level HDL based on Scala.
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When creating a data structure like this, is there any real reason to use s td_logic_vector rather than unsigned? I tend to use either signed or unsig ned for all multibit data types rather than std_logic_vector just because i t is easier to type and I've never found an issue.
-- Rick C. - Get a 1,000 miles of free Supercharging
Just the sake of strong typing. To my mind, a STD_LOGIC_VECTOR is a thing that does not have a numerical interpretation, and as such can't have arithmetic applied to it. An UNSIGNED has one and only one numerical interpretation, and as such can't consist of multiple bitfields doing different things. It's easier to verify the code if you do it that way, but nothing really essential.
-- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
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sse std_logic_vector rather than unsigned? I tend to use either signed or u nsigned for all multibit data types rather than std_logic_vector just becau se it is easier to type and I've never found an issue.
There is no such restriction on signed or unsigned. How does verifying the code change?
Rick C.
Interesting. Do you still happen to have that VHDL snippet?
Personally, my projects have usually had so few registers I haven't bothered with any generator. At least in my opinion if you have, say, less than 20 registers, then who cares.
However, now I have a project which has quite a lot of registers. I searched and found a Python script called hdlregs on Github. It's actually by the guy (Guy Eschemann) who does AirHDL now which is a payola web service to generate register files with an AXI4 slave interface.
Hdlregs takes json as input and generates docs in HTML, VHDL code and C headers. Bus interface is simple address/data/control, user interface to regs is a single record in and another one out. The script seems to have some limitations so hardly perfect but good enough for my needs. Then again, it's in Python so easy to improve. Documentation is zero apart from one example.
Make sure to read the whole thread as there is a small typo in the posted c ode. The typo is corrected in a later post.
Feel free to use RegisterWizard from Bitvis. This is freeware - so no cost .
The input is in JSON, and is easy to use by anyone. It is well documented - including examples. The generated bus interface is what we call Simple Bus Interface (SBI), whi ch is what people some year ago would have called a simple SRAM interface. If you need a more advanced interface you can just make a general wrapper.
If you download the open source UVVM (Universal VHDL Verification Methodolo gy) from Github
- Espen
Thanks. Well, it looks like it will take some work to get from the snippets to a working implementation but I'll see what I can do with it.
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