Hiding data inside a FPGA

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Hello,

  I am working on cryptographic application over VirtexII FPGAs. I
need to store a simmetric key inside a reg of the FPGA, but I dont
want that someboy could read it analizyng the bitstream. The bitstream
could not be encrypted. Has anybody experience about hide data inside
a FPGA?. Anyone knows some papers about this topic?

Regards

Javier

Re: Hiding data inside a FPGA

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Hiding a key should be easy if your "reg of the FPGA" is formed by a
non-contiguous set of flip-flops.  Unless the person reading the
bitstream
understands the register's usage within the FPGA, they could not
determine
which of the bitstream bits make up the "reg" and in what order.  Try
to avoid regular structures (like relational place macros) for your
register and either place the flip-flops randomly by hand, or set
the placement switches to ignore register ordering when you place and
route.


Re: Hiding data inside a FPGA

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A problem arises if you are making more than one device though if they need
different keys, as an
attacker could compare the bitstreams to find where the key is stored. Adding a
significant amount
of extra random data would make it harder.
Another thing you could do is store a large block of data in a RAM element, with
multiple levels of
indirection, i.e. some bits determine the location of other bits, which
determine the location of
other bits  etc., with the rest filled with random data.


Re: Hiding data inside a FPGA
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I'd say force the placement of theses regs around. And you can also make
a small logic block that "calculates" the key from apparently random data.


    Sylvain

Re: Hiding data inside a FPGA
Maybe you should think about another FPGA (e.g. without bitstream).

Otherwise I would generate the key instead of hardwireing it.
It depends on your apllication how save you need the key and how likely
it is that an attacker has access to your bitstream.

bye Thomas


Re: Hiding data inside a FPGA
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Hello
bitstrea
insid

Javier


If you use the new Lattice XP devices, the need for an external PRO

is eliminated and read back can be disabled.  They do this by havin
the Flash internal.   Just offering another way to "skin the cat"

Regards

Jeff Holle
Lattice FA
(yes, I work for Lattice


Re: Hiding data inside a FPGA
Would be nice if more Lattice FAEs would participate n the discussions
on this
board ...

Rgds
AndrE9%


Re: Hiding data inside a FPGA
Would be nice if more Lattice FAEs would participate n the discussions
on this
board ...

Rgds
André

there are people with Lattice and Actel experience around, but yes there
seem to be no public comments from anyone directly from Lattice of Actel.
This could actually be corporate policy of those companies. ?

Antti



Re: Hiding data inside a FPGA
On Tue, 09 Aug 2005 19:16:32 -0500,

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Hello,
Thank you for your answer. I am not familiar with those type of FPGAs
and I dont know the configuration mechanism. Is it possible to
on-the-field reprogram a FLASH based FPGA using a external
microprocessor connected to Internet as in Xilinx IRL scheme?

Best Regards

Javier Castillo

Re: Hiding data inside a FPGA
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yes it is.

the Actel PA3 also allows non volatile secure keys for encrypted bitstream
(I thínk that is not possible for LatticeXP)

Antti





Re: Hiding data inside a FPGA
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They use JTAG, so I suppose you could put a JTAG master in your micro.

-a


Re: Hiding data inside a FPGA
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As a possible alternative, you might want to consider ...

http://www.actel.com/products/rescenter/security/solutions/flash.aspx
http://www.actel.com/products/pa3/index.aspx

cheers,
Kris

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