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July 5, 2003, 8:54 am
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when trying to do a simulation, I get this:
Completed process "Generate Post-Translate Simulation Model".
ERROR: Hidden remap failed
Launching Application for process "Simulate Post-Translate VHDL Model".
not only it doesn't display a reason, but the program's so stupid it still
runs the simulator;
has anybody gotten a similar error?
the generate expected result simulation didn't fare much better as HDL
bencher generates an invalid script.
this happened when I started to introduce new types in the code
note to xilinx: your software guys should be locked away from computers;
just outsource the tools to people that know how to write software...
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