Help with xilinx simulation?

What does your testbench stimulus of 'a' look like? I am guessing it does not toggle and is always low. Try toggling the input stimulus and see how 'y' responds in the simulation.

-davide

The stimulus is automatically applied by the Test Bench Waveofrm wizard, it is a clock of 5 periods at 1000ns in total (5 periods). There seems to be little yellow spikes where the clock positive edges are, I don't know what these are supposed to be. I am supposed to get a clock on y as my module simple assign y

1. You should probably look up in the Xilinx documentation about what the yellow spikes are all about.
2. Take a look at the testbench code that was generated, (maybe post that up here for all to see).
3. Maybe there is some problem with your simulator.

I realize that the testbench code that you're using was generated by Mr. Wizard, but it should roughly look like the following....in fact maybe try copying the code below into your current testbench code file and comment out or delete what is there and try simulating. If the code below works then you should look for differences between it and the Mr. Wizard generated testbench code (after finding out what yellow spikes are) and try to figure out what is going on.

entity tb is end tb

architecture RTL of tb is signal a: std_logic := '0'; signal y: begin a a, y => y); end RTL;

KJ

Is this your first simulation ever? Perhaps you are not using the tools properly. You have to save the testbench, make sure that the test bench is highlighted in the source pane, (the testbench should be under the mod1), and in the process pane the Simulate Behavior needs to be clicked. I'm not an 8.2 user yet, so perhaps there is some other things to watch out for.

Then you should try y Hello all,

The fact that I am getting a simulation indicates to me that I have been using the tools correctly. The fact that the simulation is not working indicate to me that xilinx tools do not work 'out of the box' (if at all).

What am I supposed to ask?

These comment were made so that people know what I am looking at. Reading the manuals will come later, after I know the xilinx tools do work. After all, what good is it to learn a tool if it doesn't work?

up

I explained what I did, surely you can duplicate it and see what the code is ?

out

figure

OK I'll see if I can, but really, I don't want to be debugging for xilinx, this is their job. If it doesn't work, I'll wait for their next version.

The fact that the simulation is displays shows that I am using it correctly.

still y = 0

Yes. I am just trying to determine if you are looking at the right screen. When I first used 6.2, I entered the waveform using the GUI, but I did not know that I needed to save that screen, (which by the way, will show all outputs as 0), and then run the simulation from the process window, which will open another screen.

I am not running 8.2, however, I think other people would be complaining by now if they couldn't port a simple input to an output, even if it is clock.

If there is a bug, perhaps you should try an asynchonous input to an output.

Or add a dedicated clk input and try:

test:process(clk) begin if(clk'event and clk='1') then y

I'm betting that if you take the time to find out what is being indicated by the yellow spikes that it will likely be a lot clearer about what to do about it from there....just my guess

No, I don't use Xilinx for simulation, I use Modelsim.

You're assuming that the problem is with the Xilinx tools. Maybe it is (seems to), but it's not clear one way or the other.

I simply posted something that should be roughly like what Xilinx generated since you didn't post the testbench code itself. If you can run my testench code within Xilinx (or the Xilinx generated testbench in Modelsim) then this would tend to point to a problem with the Xilinx simulator....in which case, the suggestion would be to use some other simulator.

KJ