help with rising edge matching

Except in simulation, two signals *never* rise at the "same time".

A quick reality check for things like this is that if you can't do something with "real" gates and flip-flops, you can't do it in synthesizable VHDL (or Verilog) either. If you *can* do it with gates and flops, then it's trivial to express it in VHDL (or Verilog).

If you mean that you need to detect when both signals rise within a clock period (for some arbitrary clock), you can do it fairly easily. For instance, if you have a 100 MHz clock, you can detect whether the two signals rise within the same 10ns clock period. Of course, there's the usual uncertainty if one of the signals has an edge too close to the active clock edge, so you need some flops as synchronizers.

The following is completely untested. Provided with no warranty, your mileage may vary, yada yada.

entity detector is port (clk: in std_logic; a: in std_logic; b: in std_logic; e: out std_logic); -- will ouptut a high pulse for one clock end detector;

architecture rtl of detector is signal a1, a2, b1, b2: std_logic; -- dual-rank synchronizers signal ap, bp: std_logic; -- previous state begin regp: process (clk) begin if rising_edge (clk) then a1

If Eric Smith's suggestions don't get you going, what kind of accuracy do you want? What devices are you targeting? Do you really want a digital value to say they rose within the specified window or is this part of a larger aspect - such as a phase detector - where the function doesn't necessarily have to be simultaneous rise detection, but a bigger scheme... an analog signal in the end, perhaps.

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Hey Eric,

Thanks for the reply. I'll try the code out.

FPGAguy