Hi guys!!!
am working on a VIRETX-II FPGA and i am downloading the bit file by using the RBT File. i am now trying to decode a RBT file, i am so confused abt how the data are stored in those frames. i am not sure how the address of each frame and the column are written in the RBT.
Any help will be appreciated.
thanks in advance.
superman321 schrieb:
RBT File. i am now trying to decode a RBT file, i am so confused abt how the data are stored in those frames. i am not sure how the address of each frame and the column are written in the RBT.
Hi Superman,
you need need to read the documents from Xilinx. I did. All the information you need is there. It really is.
Antti
Hi Antti,
Thanx a lot for the reply, I got a lot of information from the xilinx webpage, though there still remains 1 ques, which i do not understand.
after the FDRI is loaded with no. of the words that has to be written, the frames are being loaded with data right????......
like for eg:
On a virtex - II xc2v40. 30004000 --write 0 word to frame data input reg.; type
then are 10530 line of bits....and here i do not understand how there data are arranged in frames..they do not match with description as said by xilinx.
Am i rite or i am decoding something wrong??????
if possible through some lite on this plz.
thanx 1 again.
Superman321 schrieb:
though there still remains 1 ques, which i do not understand.
frames are being loaded with data right????......
type 1. 50002922 --type 2,data words,0x2922 = 10530(decimal) = (404 frames +
1)*(26 words per frame)arranged in frames..they do not match with description as said by xilinx.
I could say the same thing I said before: read the docu.
if multiply frames are loaded the the frame addr sub-fields autoincrement. The best thing is to generate a 'debug' bitstream' then each record contains each frame and you can see the frame addresses for each frame in sequence
but, why do you need to understand that stuff ?
Antti
Hey,
thanx for the reply, i am using it for partial reconfiguration.
if i send the partially decoded file, with comments would you be able to help me a little bit more, though i have read those docs, i am kinda confused. i understand that multiple frames or the whole FPGA is being loaded.
Well thanx 1 again for all those reply.
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