I have a source code which is compiled by the Design Compiler from Synopsys. I also mapped my technology library to that, so it will generate a VHDL netlist.
My problem is that there are Components declarations and instantiations in the netlist with no architecture.
And I'd like to use this netlist as a component of my design in Altera's Quartus software.
Can someone tell me how I get this fixed.
Thanks