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Help, router can't rout all connections (XILINX)

I need help. I get this error when I rout my design for my spartan 3:

WARNING:Route:438 - The router has detected an unroutable situation due to local congestion. The router will finish the rest of the design and leave one or more connections as unrouted. The cause of this behavior might be putting too much logic into a single CLB. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such congested connections:

What can I do?

I use about 81% of the slice capacity.

Device utilization summary:

---------------------------

Selected Device : 3s200vq100-5

Number of Slices: 1570 out of 1920 81% Number of Slice Flip Flops: 1662 out of 3840 43% Number of 4 input LUTs: 2420 out of 3840 63% Number used as logic: 2412 Number used as Shift registers: 8 Number of IOs: 27 Number of bonded IOBs: 27 out of 63 42% Number of BRAMs: 4 out of 12 33% Number of MULT18X18s: 9 out of 12 75% Number of GCLKs: 5 out of 8 62% Number of DCMs: 2 out of 4 50%

Reply to
Mark
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Don't we all...

Hi Mark, I suggest you use FPGA editor to isolate the problems. If only you had a list of congested connections! Other alternatives including searching the internet for something like "The router has detected an unroutable situation". There's this newfangled thing called 'Google' (perhaps you've heard of it?) that you might use. HTH., Syms. p.s. Post a few of the listed congested connections so we can actually help you. Your FPGA is nowhere near being full. My guess is maybe you've used too many clocks in an IOB tile, but who can tell unless you post the information?

Reply to
Symon

I hit something similar some time ago when I was using incremental synthesis in Precision (feed through ISE via smartguide). The design was around 80% full but failed to route. When I turned off incremental synthesis it routed it OK. If you are not using incremental synthesis/P&R then try changing your synthesis/P&R settings.

Hans

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Reply to
HT-Lab

I have never used the FPGA editor before, but im going to read about it now. :-)

What is HTH., Syms?

Reply to
Mark

Thank you, i will try that.

Reply to
Mark

And where can I find this setting?

Reply to
Mark

What Symon said.

Plus, peruse the synthesis report (.syr) for WARNINGs that might give you a clue; e.g. related somehow to the signals or components listed..

With 5 GCLKs it is possible that you are using all 5 GCLKS in one half of the FPGA (there is a limit of 4 in each corner) but I would expect different errors there.

One other possible conflict : if you are using BRAMs as 32 or 36 wide, the Spartan-3 needs to share connections with the multipliers (this is avoided if you use twice the number of BRAMs but only 16 or 18 bits from each). Since you are using 4 BRAMs + 9 Mults this is a possible candidate, but unlikely.

Two other things to try: (1) target a larger FPGA to see if the problem is inherent in the design, or somehow related to capacity (2) run MAP and PAR with a different "cost table entry" (set the -t flag to 2 or

3..99) in case placement has just randomly painted itself into a corner.

- Brian

Reply to
Brian Drummond

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