Help required regarding PCI Master core

Hello experts,

I am a final year student and working on my senior design project. I need PCI Master core and unfortunately I cannot buy any licensed core because of their high price. I have seen opencores.org PCI bridge but it has few problems

  1. Its test bench is too complex to understand. I was expecting some black box sort of interface.
  2. Its driver is written in linux, but I have developed my software part in MS Visual C-6, soI need windows driver.

If someone has cleaned and simple version of opencores PCI core or someother PCI core please send me that at snipped-for-privacy@gmail.com. I also need driver preferrably for windows. Your timely help will enable me to solve my problems. And yes, I will acknowledge source of this PCI core and driver in my project report.

with best regards Adnan

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Adnan
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Adnan schrieb:

PCI drivers are completely independent of the PCI core used. You can use the free MEMACCESS library from zealsoft with any PCI core, including the one from open cores.

Gaisler research has a GPLed PCI core. But I doubt that the test bench is simpler than the open cores testbench.

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But what do you need the testbench for? The core has been tested. As long as you do not modify it....

Kolja Sulimma

Reply to
Kolja Sulimma

  1. If you spent a little more time trying to understand how it works, you'll see that it's not that complex at all. It's simply that the tests are quite comprehensive and hence covers quite a large number of cases.

In fact, we stripped out the 'core' functions of the testbench to create a library of routines that allowed us to write testbench scripts for higher-level PCI functionality and there really isn't a lot of code in there.

  1. As Kolja said differently, there's no such thing as an "opencores PCI driver". The core out-of-the-box does absolutely *nothing* useful other than appear as a PCI bridge to bios and/or low-level OS probing routines.

It's not until you add peripherals to the back end that you require a "driver" and this is dependent not on the bridge itself but your chosen configuration of PCI space and the peripherals you implement.

IMHO implementing the opencores PCI bridge and writing some software to talk to back-end peripherals is quite nicely weighted as a final-year design project. It's not as if you're implementing the bridge yourself.

Regards,

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Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Mark McDougall

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No, Its actually a software/hardware distributed solution for OC-48 media gateway controller (A research project won from CISCO). We have implemented a software part and hardware part. Now we need a talking interface. One thing more do any one of you guys have PCI core without wishbone, as I think I am supposed to implement wishbone master to talk with wishbone slave and wishbone slave to talk with wishbone master (Please correct me if I am wrong).

Thanks alot for your valuable opionion, I am trying hard with the testbench. I need test bench because first we need to run simulation after integrating PCI core with our logic. So that things could run smoothly on FPGA.

with best regards and a bundle of thanks Adnan

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Adnan

You'll only need a wishbone master if you're going to be mastering the PCI bus.

Otherwise you'll only need to implement a wishbone slave interface on your PCI peripherals, and that's about as trivial as you can get. For example, for a simple register with a 1-clock turn-around all you need is a clocked process that drives a qualified wb_cyc_i onto wb_ack_o.

Even requiring a master, depending on your application, really isn't a big deal. Given a core without wishbone, you'd *still* be doing the same thing anyway - it just wouldn't be wishbone complaint. And for some cores I've seen, you would actually be required to do *more* work than you do for wishbone.

No free lunches here.

As bundled, the testbench exercises the PCI core and tests for corner conditions etc. If you want to be able to simulate meaningful PCI accesses to your back-end peripherals, you'll need to extract and probably modify the functions from the testbench that perform PCI read and write transactions. You'll also have to retain the portions that configure the bridge at the start of it all.

Regards,

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Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Mark McDougall

Just a small addition: it is not difficult to mimic a 16550 UART. If you buy a 16550 based PCI serial interface card and set your PCI card to the same ID, the driver for the PCI serial card will also recognize and work with your board.

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Reply to
Nico Coesel

Hello again expert, I am not clear about one thing and this is making me confused. I have read documents but could not find what is meant by term 'images' in open cores PCI core for example when he says that PCI bridge can have 6 wishbone images, 6 targets images etc etc. What is exactly meant by this. Please explaing this term to me.

thanks in advance, regards, Adnan

Reply to
Adnan

An 'image' is a memory or I/O space map.

From the host perspective, they correspond to the PCI Base Address Registers (BARs) implemented in configuration space. There's plenty of information on these in the PCI literature.

Conversely, you have the same concept from the wishbone perspective, although you've only got memory images, no I/O images. In this case the images only come into play when bus-mastering from the wishbone side.

You've also got address translation for each of the images in either direction. This allows you to add a constant offset to each address generated on the master side as it appears on the target bus.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Mark McDougall

Hello again experts, Thanks for all the suggestions and help. I have partially understood the test bench of PCI core and was able to write my own task of PCI transaction from PCI bridge (configured as guest) to one of the behavorial model of PCI device written in test bench. Now here is the problem.

I want to write data from the master of bridge to its OWN target and read written data back. This might sound stupid but this is what I have to do. Please tell is it possible or not. IMHO it is possible. I have tried to do it in the following way but failed.

  1. I have configured all the PCI target images.
  2. I just called the task wb_single_write with target_address = `TAR0_BASE_ADDR_2.
  3. But target did not accept the data which was sent to it.

I am trying to figure it out but failed. Please, Please help me to accomplish this task. If someone wants, I can send him the test bench which I have written. Your timely help will greatly help me to solve my problems.

With best regards Adnan

Reply to
Adnan

If I understand correctly, you're trying to bus master from the wishbone side and have a PCI target respond? That's certainly possible.

What you need to do is setup a wishbone IMAGE that maps to a pci target instantiated in the testbench (IIRC two are instantiated in the supplied testbench?). So either the base address of the wishbone image is the same as the PCI base address of the target, or you use address translation (from the wishbone side).

The use the *wishbone* address as target_address, not the pci address (of course they could be the same depending on how you've set it up).

Easiest way to debug is to simulate in ModelSim and see what addresses go into the core and are coming out of the PCI bus during your call.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Mark McDougall

Hello again, There is one other question, although I am supposed to find this by myself but just to get an idea I want to ask: what is the maximum throughput I can get while running PCI opencores core at 33 Mhz in windows environment and in embedded environment where there is a dedicated PCI bus between two devices for example in a scenario where FPGA is communicating with a RISC processor via PCI bus.

with best regards, Muhammad Adnan

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Adnan

Hello experts, I got succesfull in using this core. Thanks for your help. But one question. What am I supposed to do if I want to just read (obviously I am not going to write) configuration space of of other PCI card, in the PC ENVIRONMENT, with open core PCI bridge CONFIGURED AS GUEST. Actually I cannot use open core pci bridge in WINXP environment in host mode.

regards Adnan

Reply to
Adnan

Let me get this right - you want to read another target's config space from the wishbone bus side of the PCI bridge?!?

Well, you need to do exactly what a PC host would do - probe the bus for the card in question and then map the base address of the card's config space into the WISHBONE image BAR. Obviously if you can arrange for the host PC application to supply you with the config base address then it's a little easier...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Mark McDougall

This is a bit more complicated because a PCI unit will only answer a config request if its IDSEL pin is activated. In practice I understand that IDSEL is almost always wired to some of the high bits of AD.

As for opencore's PCI core, I guess that you will have to modify it if you truly have a genuine need for reading the config space of other cards and can guarantee that you can actually make it work reliably for your design in all cases.

But wouldn't it be easier to just read the config space of other cards from your device driver and then tell your card whatever it wants to know?

Why do you even need to read the config space of other cards?

/Andreas

Reply to
Andreas Ehliar

Sir you are right, I want to read configuration space(only BARS) of another target. But here is the problem.

In the implementation of PCI bridge, you can configure it in 2 modes i.e. guest mode and host mode. Now consider test bench of PCI bridge "system.v",

IN HOST MODE: whenver it needs to generate configuration cycles it does this from the wishbone side, by writing configuration address register with values like device no, bus no, register no etc. This register is implementation in module config_space. And I can see configuration cycle in waveform. And this register is implemented under `if_def HOST, even the calls of tasks in the system.v is written under if_def host.

GUEST MODE: whenever it needs to generate configuration cycle it uses behavioral PCI module to do this.

I have tried this by removing if_def host, but it did not work.

Your timely reply will certainly help me out. With best regards. Adnan

Reply to
Adnan

I don't think using the bridge in host mode is an option in a PC...

As Andreas rightly pointed out, not only do you have to read config space of other cards, you also need to ensure IDSEL is generated.

And as we both suggested, have your host driver probe the required information and explicitly write it to your card. It is the most practical and benign solution.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, 
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Reply to
Mark McDougall

well sir, let me explain you the whole problem. Targetted application will be the embedded environment and I shall have to configure SATA controller using this opencores PCI. SATA controller talks in the language of PCI.

Fortunately, right now I have a PCI card having SATA controller, so basically this gives me an opportunity to emulate whole embedded environment just by placing SATA card and FPGA card in two slots of the same PC. I can use driver to probe the bars but I want to read BARs of SATA card with the help of opencore PCI because this is what I shall be eventually doing.

Now I want to take your opinion and suggestions in this regards. Having a nice day. Regards Adnan

Reply to
Adnan

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