help on RISC controller developed mikej

now i have the complete correct code ( i got that from open cores.org) and i could pin point the errors im uploading the whole code fist let me tell the errors when i compiled the code 1.in mux8 file im getting Warning: ELAB1_0026: mux8.vhd : (87, 0): There is no default binding for component "lut4".(No entity named "lut4" was found). Error: COMP96_0078: mux8.vhd : (84, 22): Unknown identifier "mux8_lut4". Error: COMP96_0133: mux8.vhd : (84, 22): Cannot find object declaration. Error: COMP96_0078: mux8.vhd : (83, 22): Unknown identifier "mux8_lut3". Error: COMP96_0133: mux8.vhd : (83, 22): Cannot find object declaration. Error: COMP96_0078: mux8.vhd : (82, 22): Unknown identifier "mux8_lut2". Error: COMP96_0133: mux8.vhd : (82, 22): Cannot find object declaration.

2.in mux4 file im geting Warning: ELAB1_0026: mux4.vhd : (75, 0): There is no default binding for component "lut4".(No entity named "lut4" was found). Error: COMP96_0078: mux4.vhd : (72, 22): Unknown identifier "mux8_lut2". Error: COMP96_0133: mux4.vhd : (72, 22): Cannot find object declaration. Compile Architecture "RTL" of Entity "MUX4" Compile failure 2 Errors 1 Warnings Analysis time : 0.1 [s]

3.in risc5x_xil as warning: ELAB1_0026: risc5x_xil.vhd : (189, 0): There is no default binding for component "ramb4_s2_s2".(No entity named "ramb4_s2_s2" was found).

4.in add_sub Warning: ELAB1_0026: add_sub.vhd : (76, 0): There is no default binding for component "lut4".(No entity named "lut4" was found). Warning: ELAB1_0026: add_sub.vhd : (90, 0): There is no default binding for component "mult_and".(No entity named "mult_and" was found). Warning: ELAB1_0026: add_sub.vhd : (97, 0): There is no default binding for component "muxcy".(No entity named "muxcy" was found). Warning: ELAB1_0026: add_sub.vhd : (105, 0): There is no default binding for component "xorcy".(No entity named "xorcy" was found). better the whole proram is here u ca run urself and u could debug the errors "
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pls pls pls pls reply

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sel
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If you had read the (admittedly sparse) documentation you would have noticed it is targeted by default to Xilinx architecture and instantiates directly some Xilinx primitives. In each file there is a second architecture (surrounded by --pragma translate_off / --pragma translate_on) statements which is a generic RTL version for the simulator. If you remove these pragmas, the synthesis tool will then see the generic version.

I cannot help you more as you do not say which tool is generating the warnings, or what you are trying to do. /MikeJ

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MikeJ

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