Hi,
(Sorry that if I sent this more than once. Somehow, my email client just doesn't function well.)
I'm new to FPGA world and currently working on an emulation board with 2 Virtex-5. I think to forward clock from chip A to chip B. Is that possible to make these 2 clocks synchronous ? What kind of steps, components and constraints need to be done to ensure the synchronous between these 2 FPGAs. The clock frequency is about 50-100 MHz range.
My current scheme is as following, but doesn't work properly. Any help is appreciated.
On FPGA A,
- A clock, APP_CLK (200 MHz), comes out of a DCM, which is used to mange the receiving clock from off-chip DDR2 DIMM.
- APP_CLK drives another DCM for clock synthesis of 100 MHz and 50 MHz. The feedback of this DCM is from the output of DCM itself, which may be an issue.
- Takes the 100 MHz clock to an ODDR primitive (Dedicated IOB double data rate output registers). This is suggested by Xilinx Vitex-5 User Guide.
- forward this clock to FPGA B.
on FPGA B,
- use IBUG, DCM and BUFG to generate the synchronous clock.
My concern is:
- The 2 FPGAs don't have knowledge about each other. How does these two clock synchronize to each other ?
- I put huge clock uncertainty (4 ns) with INPUT_JITTER. I hope this will compensate the latency on board.
- What IO standard and PAD's constraints is suitable for this?
One background that why I didn't choose board clock source to distribute 2 FPGAS is because we want the 100 MHz clocks of both FPGAs synchronized to APP_CLK.
Appreciate any help in advance.
Chris Kuo @ Austin, Texas