Help Needed Regarding VPR

Hi,

We need to evaluate new CLB architectures for routing area and delay. In VPR how can I specify my CLB architecture accurately. In architecture file all I could find out was that we can change number of LUTs and their input size. But in our architectures apart from LUTs we also have some extra combinational modules. Is it possible for me to specify no of transistors that my CLB takes in VPR and then let VPR do placement and routing because that will give routing area and delay according to our architecture. If yes where should I do that. I feel that currently VPR finds out number of transistors of a CLB based on number of LUTs present but I was unable to figure out where does it use this information after going through the code.

Kindly help me if someone has gone through the code or has modified it.

Thanks and regards,

VPR does not count the transistor area used inside a logic block. It counts the area in the routing per tile and prints that out. To get a total area, you have to add in the area of the logic block, not including the routing or routing interfaces (output pin drivers & muxes before input pins).

So basically just create a program or spreadsheet or layout to estimate the area of your new logic block. Then add in the routing per tile area from VPR, and use that to compute a height & width for a tile. That defines the physical length of your routing wires, which then lets you compute the R & C of your various routing wires. That must be entered in the VPR .arch file to get accurate timing results with your new CLB.

I have a separate program from VPR that computes the area of "cluster-based logic blocks" (they are much like generalized Altera LABs). If your logic block fits into that category, let me know and I can email you that program. Some of the papers on my "academic" web site

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describe what cluster-based logic blocks are, if you need more info.

Hope this is clear.

Regards,

Vaughn Betz [v b e t z (at) altera.com]