1. Home
  2. Field-Programmable Gate Arrays
  3. Help needed regarding addition of Custom IP core to EDK

Help needed regarding addition of Custom IP core to EDK

Hey Folks ,

I face a strange problem of adding my custom IP to the EDK project .

My custom IP has two parts : a Small FSM and a Fifo Generated using coregenerator ( This was generated as EDN and the HDL is verilog) .

I added my Custom IP to the Base System which has a ppc.

I went into /pcores/mY_IP/hdl/Verilog and put my design.

created /pcores/mY_IP/netlist and put all the EDN Files

Then I defined my Black box Definition

And added the various other options such as OPTION STYLE = mix, OPTION Ngc_build = true etc,.

I get this weird problem If I click Generate netlist :.

ERROR:MDT - File not found in any repository 'Fifo_test_v1_00_a/hdl/vhdl/simpl_tx.vhd'

It defaultly goes and searches in the vhdl directory instead of verilog directory .

Can anyone give me pointers abt this problem ?

Is there any workaround that I synthesize the design in ISE and ask the EDK to use the NGC which would give me more flexibility ?

Reply to
karthiknatrajan
Loading thread data ...

Is your pao file implemented correctly? That's the first thing that popped into my head.

So is the simpl_tx (that is how you spelled it above - maybe that's the problem?) a verilog file? As far as I know, the pao needs to specify that in the analyze order. There's no reason that you can't have a FIFO core ngc and HDL files in the same IP.

Reply to
motty

Hi ,

Yes I have included this in the periperal analyze order (Pao ) .

The problem is When I try to add a coregen IP ( I generated the IP with Verilog becoz I was more comfortable with that) to my EDK , I followed all the necessary steps.

EDK defaultly thinks that I have the generated the IP using Coregen using VHDL option and goes to the directory :

Fifo_test_v1_00_a/hdl/vhdl/simpl_tx.vhd

But It shoud actually go to the directory

Fifo_test_v1_00_a/hdl/verilog/simpl_tx.v

I d> Is your pao file implemented correctly? That's the first thing that

Reply to
karthiknatrajan

The EDK will search the libraries you list in the pao. I do all my cores in verilog and don't ever have problems.

I don't understand what you mean by the EDK going 'defautly' to the vhdl folder. Is simpl_tx the fifo? If it is, put the verilog file (generated by core gen) in the hdl/verilog folder and include it in the pao. Then put the ngc in the netlist folder and include it in the bbd file.

Somehwere/somehow the EDK thinks it is searching for a VHDL file called simpl_tx...and I really don't think that is in a script anywhere....at least one that isn't generated via files you have access to in the core.

Post the pao (at least to make me shut up about that). I can't think of why your core is behaving badly. But maybe if it was in front of me I'd understand better.

Reply to
motty

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.