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Help needed

Hi,

I have a IP block which is responsible of receiving all different kinds of external inputs and condition them. Once received siganls are validated than i need to pass them to different IPs and also to the centralized memory place (like BRAM) so they can be shared with the processor.

Here is my problem:

  1. If the received signal needs to be consumed by two or three different IPs how can i do that. I cannot use the BRAM for that as prefered way is to have them connect directly to signal processing IP.

So Signal Processing Block ---> User IP(s)

  1. What are the methods to hardcode the connections between the two user IP. I mean without using bus. Just Point to Point connection. I think it has to do with the net names but need some more explanation on that how to do.

Thanks

Fizzy

Reply to
Fizzy
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I don't really understand what's being asked but...

It sounds like you want to create IP blocks that both "talk" to software via a bus (probably OPB) and also connect directly to other IP modules. And I assume you are working in the EDK. The import peripheral wizard tool will create the proper Verilog/VHDL wrappers for your IP. Within the user logic module, you will specify all the I/O that you want for a particular IP block. If you want to connect it entirely to the OPB, meaning only software controlled, then you would not specify any I/O signals. You would instantiate your module inside the user logic and just pass signals back and forth via slave register writes/reads.

However, it sounds like you want both software and hardware signals. The I/O that you specify in the user logic wrappers will eventually become the I/O signals that the IP module has available. Inside the EDK these signlas will show up and you can connect them directly to any other IP that you wish.

There is some good documentation in the EDK install directory. I hope this helps. If I totally missed the question, let me know.

Reply to
motty

Thanks for replying...

Can you guide me to some examples or literature which can tell me how to connect to IP directly.

Reply to
Fizzy

There is documentation in the EDK installation directory...specifically how to create user IP cores and how to connect them to the OPB bus. The wrapper files that instatiate the OPB logic are the key. You have to instatiate your core in one of those (user_logic.v or vhdl) and create ports that connect to your IP instantiation. When you make the port connections to your instantiated core, you can either specify one of the external ports you have declared in the user_logic or you can specify a slave register bitfield. The external ports are mapped into the upper level wrapper file (vhdl) and you must specify them in the mpd file. Once you do this, those ports are available in the EDK whenever you pull in your core.

It's not trivial, but it will make sense once you do it a couple times. Then you can use software to write to the slave register for your core and connect the external signals however you want to...even bring them out to the FPGA pins if needed.

Hope that makes some sense.

Reply to
motty

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