Help! Micriblase + plbv46_pci in Virtex5

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I am connect plbv46_pci(in slavemode) to Micriblase. F7%ut in
Plase&Route ISE give warning:

WARNING:Route:436 - The router has detected an unroutable situation
for one or more connections. The router will finish
   the rest of the design and leave them as unrouted, The cause of
this behavior is either an issue with the placement
   or unroutable placement constraints. To allow you to use FPGA
editor to isolate the problems, the following is a list
   of (up to 10) such unroutable connections:
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC3_MapLib_replicate11/REFCLK
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC0/REFCLK
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC1/REFCLK
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC2/REFCLK

And write:


Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Loading device for application Rf_Device from file '5vlx50t.nph' in
environment
D:\Xilinx92i.
   "system_stub" is an NCD, version 3.1, device xc5vlx50t, package
ff665, speed
-1

Analysis completed Mon Jan 14 18:43:01 2008
----------------------------------------------------------------------------=
----

Generating Report ...

Number of warnings: 0
Total time: 27 secs

Process "Generate Post-Place & Route Static Timing" completed
successfully

But in Generate Programming File I have Error:

Started : "Generate Programming File".
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   system_i/PCI_Bridge/PCI_Bridge/I_plb2pci_bridge/I_slv_ipifv3_bridge/
I_slv_ipi
   f2pci_fifo/I_slv_ipif2pci_fifo_cntrl/Wr_Addr_All_zeros_strobe is
sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin
to
   control the loading of data into the flip-flop.
INFO:PhysDesignRules:1505 - Dangling pins on
   block:<system_i/microblaze_0/microblaze_0/Performance.Data_Flow_I/
MUL_Unit_I/
   Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/
Using_Virtex5.DSP
   48E_I1/system_i/microblaze_0/microblaze_0/Performance.Data_Flow_I/
MUL_Unit_I/
   Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/
Using_Virtex5.DSP
   48E_I1>:<DSP48E_DSP48E>.  When the DSP48E AREG attribute is set to
1 the CEA1
   input pin should be tied GND to save power.
INFO:PhysDesignRules:1509 - Dangling pins on
   block:<system_i/microblaze_0/microblaze_0/Performance.Data_Flow_I/
MUL_Unit_I/
   Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/
Using_Virtex5.DSP
   48E_I1/system_i/microblaze_0/microblaze_0/Performance.Data_Flow_I/
MUL_Unit_I/
   Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/
Using_Virtex5.DSP
   48E_I1>:<DSP48E_DSP48E>.  When the DSP48E BREG attribute is set to
1 the CEB1
   input pin should be tied GND to save power.
ERROR:PhysDesignRules:9 - The network <GLOBAL_LOGIC0> is only
partially routed.
ERROR:Bitgen:25 - DRC detected 1 errors and 1 warnings.

Process "Generate Programming File" failed

My ucf file: (use XC5VLX50T-1ff665)

NET "iClock77"  LOC 3D% "E13" ;
NET "iClock125"  LOC 3D% "D14" ;

NET "PCI_AD[0]"  LOC 3D% "E5"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[1]"  LOC 3D% "E6"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[2]"  LOC 3D% "B4"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[3]"  LOC 3D% "E8"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[4]"  LOC 3D% "E7"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[5]"  LOC 3D% "D9"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[6]"  LOC 3D% "B5"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[7]"  LOC 3D% "D11"   |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[8]"  LOC 3D% "E11"   |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[9]"  LOC 3D% "B6"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[10]"  LOC 3D% "F13"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[11]"  LOC 3D% "E12"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[12]"  LOC 3D% "E15"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[13]"  LOC 3D% "B7"   |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[14]"  LOC 3D% "E17"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[15]"  LOC 3D% "F15"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[16]"  LOC 3D% "E21"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[17]"  LOC 3D% "D13"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[18]"  LOC 3D% "D21"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[19]"  LOC 3D% "D15"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[20]"  LOC 3D% "D24"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[21]"  LOC 3D% "D16"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[22]"  LOC 3D% "C24"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[23]"  LOC 3D% "B14"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[24]"  LOC 3D% "D25"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[25]"  LOC 3D% "B17"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[26]"  LOC 3D% "D23"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[27]"  LOC 3D% "C18"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[28]"  LOC 3D% "D26"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[29]"  LOC 3D% "B19"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[30]"  LOC 3D% "C26"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_AD[31]"  LOC 3D% "B20"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_CBE[0]"  LOC 3D% "D10"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_CBE[1]"  LOC 3D% "E18"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_CBE[2]"  LOC 3D% "B12"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_CBE[3]"  LOC 3D% "B16"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "fpga_0_PCI_CLK_FB"  LOC 3D% "E20"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_DEVSEL"  LOC 3D% "B10"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_FRAME"  LOC 3D% "C22"   |  IOSTANDARD 3D% LVCMOS25 ;
#NET "PCI_GNT_A"  LOC 3D% "C23"  |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_IDSEL"  LOC 3D% "B15"   |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_IRDY"  LOC 3D% "B11"    |  IOSTANDARD 3D% LVCMOS25 ;
#NET "PCI_IRQ"  LOC 3D% "B26"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_PAR"  LOC 3D% "D8"      |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_PERR"  LOC 3D% "B9"     |  IOSTANDARD 3D% LVCMOS25 ;
#NET "PCI_REQ_A"  LOC 3D% "B21"  |  IOSTANDARD 3D% LVCMOS25 ;
#NET "PCI_RST"  LOC 3D% "B25"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_SERR"  LOC 3D% "F18"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_STOP"  LOC 3D% "F19"    |  IOSTANDARD 3D% LVCMOS25 ;
NET "PCI_TRDY"  LOC 3D% "F20"    |  IOSTANDARD 3D% LVCMOS25 ;

NET "LedGreen"  LOC 3D% "H21"  ;
NET "LedRed"  LOC 3D% "G21"  ;
NET "LedYellow"  LOC 3D% "G20"  ;
NET "LedBlue"  LOC 3D% "H19"  ;

INST "*XPCI_IDC0" LOC 3D% "IDELAYCTRL_X0Y4";
INST "*XPCI_IDC1" LOC 3D% "IDELAYCTRL_X1Y4";
INST "*XPCI_IDC2" LOC 3D% "IDELAYCTRL_X1Y3";
INST "*XPCI_IDC3" LOC 3D% "IDELAYCTRL_X1Y5";

Re: Help! Micriblase + plbv46_pci in Virtex5
May I ignore this warning?

WARNING:Route:436 - The router has detected an unroutable situation
for one or more connections. The router will finish
   the rest of the design and leave them as unrouted, The cause of
this behavior is either an issue with the placement
   or unroutable placement constraints. To allow you to use FPGA
editor to isolate the problems, the following is a list
   of (up to 10) such unroutable connections:
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC3_MapLib_replicate11/REFCLK
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC0/REFCLK
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC1/REFCLK
     Unroutable      signal: GLOBAL_LOGIC0      pin:
system_i/PCI_Bridge/PCI_Bridge/PCI_CORE_V5_generate.pci_core/
IDELAYCTRL_4.XPCI_IDC2/REFCLK


Re: Help! Micriblase + plbv46_pci in Virtex5
Quoted text here. Click to load it


No, not if you want to get a bitstream.

You have a problem with how you are dealing with the IDELAYCTRL
blocks. It has been a while since I dealt with the IDELAYCTRL blocks
in our designs and this is from memory so the details may be a bit
off. I am also using the V4s so it may be different for the V5.

First go back and reread the IDELAY section of the V5 documentation.
On the V4, there was two options on how we could deal with the IDELAY
controllers. We could either instantiate all of them, or either one or
none of them (I don't remember which) and let the tools deal with the
rest. By all of them, I mean every one of them in the FPGA, not just
every one that you are using.

From your UCF, it looks like you are using four of the IDELAYCTRL
blocks. My guess about the problem you are having is that you have
instantiated and placed those four, and not done anything about the
other IDELAYCTRL blocks in the FPGA and the tools are unhappy about
that.  If that is the case, instantiate all of the IDELAYCTRL blocks
in the FPGA.

But like I said, it has been a while since I had to deal with this so
reread the IDELAY section of the V5 documentation with this suggestion
in mind.

Regards,

John McCaskill
www.FasterTechnology.com

Re: Help! Micriblase + plbv46_pci in Virtex5
Thank! If I send my projekt to you e-mail, can you see his? I fight at
this problem 3 days....:) Projekt compiled succesful if ignored this
warning (if disable "run design rules checker(DRC)"). But in EDK when
bild softvare - give error analogous that:

http://groups.google.ru/group/comp.arch.fpga/browse_thread/thread/6c22e816b4b65c7d/1576b93ac8fc645e?hl=ru&lnk=st&q=region+ilmb_cntlr_dlmb_cntlr+is+full#1576b93ac8fc645e

send me letter if you can see my projekt (projekt consist from
microblaze+GPIO_LEDS+PCI_Bridge)

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