Dears
Can anybody help me in realizing below Mathlab code to VHDL This is just a deceptive one, Tried in both DSPBuilder or SystemGenerator.
If not possible by tool ,can anybody help me in hinting in Converting this to VHDL.
Have many doubt's in DSPBuilder How to insert the FOR loop in DSP Builder and Variable and assignment's realized form it. Thanks in advance. Satish
---------mathlab code-------------
% Inputs : Signal : 256 Samples, 16 bits each % constants Any value may be assigned to them for time being % XP : 256 * 16 Bits () % YP : 256 * 16 Bits % A % B % C % Rmin % Rmax % dR % D
% Array : array 65536*16 or block RAM
fftSig = fftshift(fft(fftshift(signal)),512));
for k = 1:256, for k2 = 1:256 tst =sqrt(( XP (k2)-A).^2+ (YP(k)-B)^2 +C^2); if (tst > Rmin & tst < Rmax-dR); IL = (tst ?Rmin)/dR+1; Ind = floor (IL); Q =IL-Ind; px = fftSig(Ind)+Q .*? (fftSig(Ind+1)-fftSig(Ind)); INDEX = k + (k2 ? 1)*256; ARRAY(INDEX)= ARRAY(INDEX) +px.*exp(-j*D*tst); % j= sqrt(-1) End End end
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