help:dual-edge flip-flop possible using Verilog?

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Im designing a module working as an fm0-encoder, the clk and max
datarate of which are both 640KHz. It is not complicated when the
datarate is lower than 320K, the half of clk. But when the datarate of
640K, the clk frequency, is concerned, the problem comes that I have to
change the state at both the rising and falling edge of the clk. Now I
am using a mothod via combinational output, which is not so good and
expansible as registered output using an FSM. I think that an FSM using
DET(dual-edge flip-flop) would work, but I am not sure wether it is
recommandable to use det and I don't know how to describe a det using
synthesizable Verilog?
It would be appreciated very much if some of you can
*comments about the det method,
*the methed about how to describe a det flip-flop

thans a lot for any help!


Re: help:dual-edge flip-flop possible using Verilog?
yyqonline schrieb:
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It is not difficult to driscrobe dual-edge flip-flop in an HDL.
The real question is: Can you build them in your target technology?
Most FPGAs do not have them and most standard cell libraries do not
have them either.

Kolja Sulimma

Re: help:dual-edge flip-flop possible using Verilog?

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Do you really mean KHz and not MHz?  If this is not a typo I would
suggest using a much faster clock to run an FSM that samples the
640KHz clock and uses edge detection (XOR on two stages of
flip-flop) to enable data transfer.

If you're really talking MHz, modern FPGA's have ways to deal with this
at the I/O buffer (double-data-rate flip-flops).

Generally multi-edge flip-flops are not synthesizable, but if the part
has them, they can be instantiated.  i.e. you can't just write:

always @ (posedge clk or negedge clk)
 ...

and expect the synthesis tool to generate useful RTL.


Re: help:dual-edge flip-flop possible using Verilog?
\quote
Do you really mean KHz and not MHz?  If this is not a typo I would
suggest using a much faster clock to run an FSM that samples the
640KHz clock and uses edge detection (XOR on two stages of
flip-flop) to enable data transfer.
If you're really talking MHz, modern FPGA's have ways to deal with this

at the I/O buffer (double-data-rate flip-flops).
Generally multi-edge flip-flops are not synthesizable, but if the part
has them, they can be instantiated.  i.e. you can't just write:
always @ (posedge clk or negedge clk)
 ...
and expect the synthesis tool to generate useful RTL.
\quote

Now we are using FPGA for verification while at the end this circuit
will be implemented by asic tech, so the system clock is fixed at
640Khz.
I am not sure whether
always @(posedge clk or negedge clk)
is synthesizable.


Re: help:dual-edge flip-flop possible using Verilog?
I think the only device that supports this are the Xilinx CoolRunner II.

This Should work:

always @(posedge Clk or negedge Clk)
begin
    if(Rst == 1)
        Cnt <=0;
    else
        Cnt <= Cnt +1;

end

yyqonline wrote:
Quoted text here. Click to load it

Re: help:dual-edge flip-flop possible using Verilog?
I suggest we wait for the original poster to clarify.
I think there is no real need for a dual-edge triggered flip-flop.
Definitely not at the low frequenciesmentioned.
There is also a simple circuit that XOR differentiates the clock, thus
generating a clock pulse at both the rising and the falling edge. (See,
among others, at "Six Easy Pieces" in TechXclusives)
Peter Alfke


Re: help:dual-edge flip-flop possible using Verilog?
Thanks a lot for replying.
\quote
There is also a simple circuit that XOR differentiates the clock, thus
generating a clock pulse at both the rising and the falling edge. (See,

among others, at "Six Easy Pieces" in TechXclusives)
\quote
I have found the circuit and thanks for information.
I am checking the stability of this circuit.
If this circuit is reliable, I think this may be a good idea.


Re: help:dual-edge flip-flop possible using Verilog?
The circuit is reliable, although the generated pulse width is
determined by gate delays. But it is self-compensating, since the clock
pulse will not end until the flip-flop has toggled. It's kind of
clever, if I am allowed to say so...
Peter Alfke


Re: help:dual-edge flip-flop possible using Verilog?
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It probably needs some care, to ensure CLK_min times are ok ?

eg if you drive a large clock tree, it would be better to not
use a local FF clk, and then buffer, but to buffer, and then
FF.CLK from the CLK tree output, with optional additional
delays, if you want even more margin.

Quoted text here. Click to load it
  Yes, I recall a similar [XOR-Q] clock scheme many, many years ago, on
a circuit ( from HP?) for Biphase decode.

-jg



Re: help:dual-edge flip-flop possible using Verilog?
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This circuit really shouldn't be advocated for FPGA use.  It is an
asynchronous hack.  It would not get through a serious design review
except in extenuating circumstances.  Generally speaking, depending on
gate delays for circuit operation is bad practice.  This particular
circuit has potential problems with pulse width and is dependent on the
clock duty cycle for proper operation.  (Yes, I can remember using it a
long long time ago with some TTL designs, but then those designs also
had one-shots in them).  Another problem with it, is the static timing
analyzer and timing driven place and route do not consider the
asynchronous behavior of this circuit.

Re: help:dual-edge flip-flop possible using Verilog?
\quote
This circuit really shouldn't be advocated for FPGA use.
\quote
Thanks for help.
I am not sure how to realize the same function (double the frequence of
the clk)?
Maybe some of the FPGA's architecture support this.
Then I would like to know how this circuit perform as far as asic is
concerned?


Re: help:dual-edge flip-flop possible using Verilog?
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That's exactly where I'd expect to run into problems.  It's not too
difficult to characterize it in a particular FPGA, but the performance in
the FPGA tells you almost nothing about what to expect in an ASIC.

Using asynchronous logic in an FPGA leads to trouble, and doing it then
expecting it to work the same in an ASIC could lead to a disaster.

As others have suggested, unless your transition rate is extremely fast,
you're much better off using a clock at a higher rate, a synchronizer
(two chained FFs), another FF, and an XOR between the D and Q of that
last FF.  That will get you a pulse with a width of one clock cycle
every time the input transistions.

Re: help:dual-edge flip-flop possible using Verilog?
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Hi Peter,
Clever the circuit may be, but I'm concerned that it may not be a good idea
to suggest this circuit to a guy who appears to be just starting out using
FPGAs. I agree it's a quick and easy answer to get him going, but he should
be made aware of the pitfalls of this circuit. For one, how will the timing
analyser cope with this? Also, how does he control the skew between input
and output? In your article you rightly say "This asynchronous circuit ...
should only be used as a tool of last resort.", so it should be in CAF
threads as well!
I'd strongly suggest the OP use a DCM or PLL or whatever his FPGA vendor
supplies to double his clock. He should wait until he's really desperate
before resorting to asynchronous tricks, no matter how clever they are!
Just IMHO!
Cheers, Syms.
p.s. If the goal is to achieve a frequency doubled clocking signal, would
the "six easy pieces" asynchronous circuit be improved by inserting a GBUF
at the output of the XNOR gate?



Re: help:dual-edge flip-flop possible using Verilog?

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Peter,

Newbie question - I remember seeing an edge detector made up from a
single XOR gate and a few inverters to add a propagation delay, but no
registers.

Would such a circuit be equivalent to yours?  Any pros/cons either way?

Regards,
Paul


Re: help:dual-edge flip-flop possible using Verilog?
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The idea of the register, is you get some register-dependance time into
the system, as the CLK will eventually be used to CLK registers - but
otherwise the ideas are similar.

The risk I see, is on large CLK trees, and very nimble registers - you
really need to get the CLK tree delay 'into the loop'


If the OP has a 640KHz SqW signal, and wants to keep it low risk,
simple to analyze, and avoid the complexity of faster clocks, he could
use 1 x  74HC1G97/1G98  Single Gate logic device externally, Wired as a
XOR or XNOR, with a RC delay on one IP of 100~200ns. ( ie as above )
These devices have Schmitt inbuilt.

Use the leading edge as CLK, as the trailing edge will be RC determined,
and it will move slightly on each 'phase' with HL and LH thresholds.
Choose XNOR or XOR gate, depending on which edge you require.

-jg


Re: help:dual-edge flip-flop possible using Verilog?
I have found that there is "clock high time violation" while timing
verification using Altera QuartusII, with device "flex10K". I wonder
whether this is caused by the pulse width, depending on gate delay, not
long enough for driving FSM.
Best Regards,
YuQing, Youth


Re: help:dual-edge flip-flop possible using Verilog?

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Yes, see my earlier comment about CLK_min, that meant not FREQ,
but the HI and LOW minimum times that all clocks have.
Such a circuit will generate needle pulse clocks, so you will
need to watch the Min pulse widths.

-jg



Re: help:dual-edge flip-flop possible using Verilog?
The circuit is reliable, although the generated pulse width is
determined by gate delays. But it is self-compensating, since the clock
pulse will not end until the flip-flop has toggled. It's kind of
clever, if I am allowed to say so...
Peter Alfke


Re: help:dual-edge flip-flop possible using Verilog?

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*blush* gee thanks, I first put forward this idea in 1973 to a UK
electronics mag, I believe I received about £150 for the article way back
then!

Slurp



Re: help:dual-edge flip-flop possible using Verilog?
Thanks for putting forward so good a circuit, which is one of the most
wonderful design I have ever learned!


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