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Help : Code works in synthesizer (silos), but warnings w/ webpack

So I'm a newbie to DPL, though I'm experienced w/ microcontrollers. I wrote code for a CPLD (xilinx target, though it can change if needed) that is supposed to run an A2D at high speed, communicate via SPI, and take the data and convert it to a manchester-encoded stream and output that. It seems to work fine in the simulator that I'm using (a trial version of silos came with the veriolog book I bought), but I'm getting warning with xilinx webpack. Also, when I run the synthesize option, it never finishes - just sits there spinning for awhile. I'm using the

6.3v of webpack as that's the version that works with the programmer I have, but I'm tempted to insall 7.0 just to see if that works any better. I'll proivde the errors I get, followed by a copy of the code I wrote. The clock (clk) is supposed externally generated, though I'm not sure how to implement it other than the way I did. I also rely heavily on delays in sending out the initalization strings - I'm not sure how it'll be implemented in the CPLD. There are only 64 flipflops in the target cpld that I want to use, so storing the init strings in flip-flop memory seemed wasteful.

Any help, or pointers to good docs would be great! Thanks in advance, Reza

Analyzing top module . WARNING:Xst:854 - a2d.v line 22: Ignored initial statement. WARNING:Xst:916 - a2d.v line 32: Delay is ignored for synthesis. WARNING:Xst:854 - a2d.v line 35: Ignored initial statement. WARNING:Xst:916 - a2d.v line 47: Delay is ignored for synthesis. WARNING:Xst:905 - a2d.v line 44: The signals are missing in the sensitivity list of always block. WARNING:Xst:916 - a2d.v line 58: Delay is ignored for synthesis. WARNING:Xst:916 - a2d.v line 59: Delay is ignored for synthesis. WARNING:Xst:916 - a2d.v line 60: Delay is ignored for synthesis. WARNING:Xst:915 - Message (916) is reported only 5 times for each module.

module a2d(sck,dout,din,cs,tx); output sck; output dout; input din; output cs; output tx;

reg [31:0] wData = 0 ; reg wPointer;

reg sck; reg dout; reg cs; reg tx;

reg clk; reg outClock = 0; reg init; reg [3:0] bit; reg [3:0] bit2;

initial begin clk = 0; sck = 1; wPointer = 0; #10 init = 1; $monitor("data=",wData[3:0]); end

/* TEST CLOCK */ always #1 clk = ~clk;

initial begin cs

Reply to
Reza
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You have a couple of things to straighten out here (I didn't check your logic for you, I just looked at a few constructs).

The biggest mistake you've made is that you mixed your logic with your test bench. Xilinx has no way of knowing which is which since they're both written in verilog. What you need to do is put all of your logic (the stuff that will go into the CPLD) in one file and then instantiate that logic in your testbench.

I'll go through a couple of problems here:

  • Delays are always ignored for synthesis. They shouldn't be needed in your logic. If they are, it is probably flawed logic, or perhaps an ugly hack to get around some other problem.
  • Initial blocks are ignored for synthesis (usually, though this is not necessarily the case). You should use either an asynchronous reset or a synchronous reset instead.
  • The following logic is bad since it is a combinational block that does not have all inputs declared.

/* GENERATE SCK WHEN outClock HIGH */ /* SCK = CLOCK/8 */ always @(clk) begin if (outClock == 1) begin sck = !sck; #4; end else sck = 1; end

For this block, you must get rid of the delays and add sck to the sensitivity list, but this logic will still not work. You can either have two clock domains, one for sck and one for clk, or you can make a state machine that outputs an enable bit for other logic. For example:

reg [2:0] dly_count; reg enable_sck;

always @ (posedge clk or negedge rst) begin if(!rst) dly_count

Reply to
gallen

Reza -

The first thing you must understand about Verilog is that some of its constructs are synthesizable, other are not. These latter constructs such as 'while', 'repeat', 'wait', 'initial' are in the language purely for simulation. These constructs cannot be synthesized. So you need to learn what constructs can be used for designing your CPLD and which ones can only be used in the testbench.

Next, you need to separate the testbench code from the CPLD logic. In the testbench, instantiate the actual design. When you want to synthesize, only give XST the actual design to work on, not the design and testbench.

Next, you need to understand about logic design, ie, how do flip flops really work, how to do synchronous design for timing analysis, etc.

You should look at some examples of other peoples work. Try Opencores.org.

Good luck!

John Providenza

Reply to
johnp

Thanks for the excellent help. Though now I'm quite irritated at the $80 verilog book that I bought - it didn't differentiate at all between the constructs that are test-bench specific, and the ones that I could use for the design. It also didn't indicate any problems with using delays in the code.

And most all that code except the part labeled 'TEST CLOCK' is all supposed to be functional logic to be implemented.

So it sounds like I'll have to re-write the whole thing. I'll look at some of the sites you referred me to. I also dont mind buying another book on the subject if you have any recommendations.

Thanks! Reza

p.s. I'll be posting again soon

Reply to
Reza

Reza -

I should have mentioned that Opencores.org has a SPI module.

I've never used it, but it may be educational to look at.

In terms of books, I've not seen any Verilog books that I thought were worthwhile. I've given up looking.

John Providenza

Reply to
johnp

The only verilog book that I use these days is the Thomas and Moorby book. It's very expensive and it wouldn't be particularly useful to you for synthesis purposes. It's really about the language itself which was designed for simulation. Synthesis is a different ball game entirely.

Here's some general advice about synthesis:

If you can't visualize the hardware being produced, you probably shouldn't code it yet. Remember that behavioral models probably won't work, and even if they do, they won't work well, or be even close to optimal.

The best place to start for learning synthesis, is to make a simple combinational circuit, followed by a complex one, followed by a simple register, followed by a state machine.

A couple simple combinational circuits might be: assign out = a & b; //and AND gate assign out = s ? a : b; //a 2 to 1 MUX assign out[3:0] = a[2:0] + b[2:0]; //a 3-bit adder

A complex combinational block uses an always statement for combinational purposes: reg out; always @ (ina or inb or inc or ind) begin out = 1'b0; if(ina) out = inb; if(inc) out = ind; end

A simple register (or flip-flop) is like this: reg q; always @(posedge clk) q

Reply to
gallen

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