For my design I must use two DCMs in series. How do I best use the CLKIN, RST, CLKFX and the LOCKED pin of the DCM?
Should i AND togheter the CLKFX and LOCKED before connecting it to the CLKIN of the following DCM?
I read that the CLKFX can give glitches, spikes, or other spurious movement when LOCKED is low. How should I do to avoid these entering the rest of my design that are clocked from the second DCM?
Tool, Connect the LOCKED signal from the first DCM to the reset of the next DCM via an inverter. HTH, Syms.
BTW, I'm not sure that cascading DCMs, especially when you're using the CLKFX output of the first DCM, is such a bright idea. Try searching the CAF archive for more info. Include 'jitter' in your keywords. If you post your specific application, someone clever/experienced will probably suggest an alternative that'll save you from a world of hurt. Syms.
two DCMs in series. How do I best use the CLKIN,
Don't worry about glitches, spikes, etc. while the DCM reset is asserted. No need to add an AND gate to the clock. In fact gating the clock is really bad practice in an FPGA in general. The only reasonable clock gating scheme in the Spartan 3 series is to use the BUFGMUX as a clock multiplexer. Even so, I'd be very careful when connecting DCM's in series. Why do you need to do it? Is it just to get the right frequency or are you expecting some phase relationship to the external clock signal at the output of the second DCM? Remember that DCM's, even the CLKFX portion, are not really phase-locked loops. Jitter will only add as you go through the system. More layers give more jitter and less jitter tolerance.
Just my 2 cents, Gabor
Thank you Symin and Gabor. I will do that. And I added a BUFGMUX to the output of the second DCM.
This is for generating a very special frequency from a 30MHz input clock.
The inverter method didn't work in simulation. I put an BUFGMUX there also.
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