help! ACTEL PROASIC PLUS clock buffer

Hi!, I have a big problem:

I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 global pin (4 GL macro), I need put a clock in a global buffer but I can=B4t because I have others signals with highest fanout. what can I do?

thanks

ch

Reply to
merche
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Explain your real problem. Do you need more global inputs or is it a problem of synthesis? Then instantiate a GL Buffer for the clk in your code

Reply to
Thomas Stanka

thanks Thomas Stanka! But...

In my code I have instantiated a GL Buffer (is a fast clock). But in the synthesis: the log say...

Automatic dissolve during optimization of view:work.w_r9(w_r9) of GL2(GL)

then, others signals with highest fanout promoted to global buffer. This synthesis is made with Synplify.

I don=B4t know how change this automatic options.

Reply to
merche

There exist no GL2 in the APA library AFAIK. Try GL25 instead. Instantiating the clk-Buffer in code should work for Synplify.

If nothing helps, you could edit the edif netlist to get a clk-buffer for the clk input, but this should be done _very_ carefully.

bye Thomas

Reply to
Thomas Stanka

bal

=B4t

GL2 is the name instanciated, the entity is a GL33. I put in the global pin, but in the chipplanner I see that don=B4t use de global macro, becouse the tool (sinplicity) put other signal. the edif netlist is only for the pins (external pad)?

Reply to
merche

If you have Synplicity why not let it infer the buffers? You shouldn't have to instance any buffers in your code.

-- Mike Treseler

Reply to
Mike Treseler

Thats right. Unfortunately I don't know how to force synplicity to choose the right buffer without constraining it in the code for those designs synplicity chooses the wrong buffer. In the APA technology you have global nets for inputs with high fan- out like clock or reset. But sometimes you have to specify which four nets should be threated as global nets.

bye Thomas

Reply to
Thomas Stanka

lobal

=B4t

our

You shouldn't mix up the tools. Synplicity is the synthesis tool building a netlist (edif) out of your code. If the edif netlist contains a GL33 for the input, you could place it with Actel Chipplanner. If not, you couldn't place a global buffer, because it is not there.

bye Thomas

Reply to
Thomas Stanka

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