Hi, I have a DDR input which every now and then gives me a nonfunctional implem= entation due to unlucky input data clocking. Thought I would try to use the= variable delay input elements with the S control input, but I only got err= or message from map that I did not connect to IO as expected.
I have instantiated the IOB_DLY_ADJ between the top level pin name recorded= in the ucf file and the input pin of the IDDR2 buffer in VHDL.
D >-- (I)IOB_DLY_ADJ(O) --> (D)IDDR2(Q0/Q1) =3D> internal DDR
Without the IOB_DLY_ADJ the design feeds data, but sometimes I am unlucky w= ith my timing.=20
In the ucf file I have NET "D" LOC =3D "AB2" |IOSTANDARD =3D "LVTTL" |IOBDELAY =3D "IFD";
According to the spartan3-hdl.pdf the delay buffer is supposed to be instan= tiated, but maybe for some reason, the original IBUF is still used. I have = not been able to find much more info on this in Xilinx docs.
--=20 Svenn