handshacking between modules, best practices ?

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Hi,


Last weekend, I was continueing on my small project to use a FPGA as  
DAC. I now use a hardware DAC (tlc5615).


So I have two modules, a top-level module for the DDS and an additional  
module to drive the TLC. I have two signal for handshacking ("load" and  
"done").
At a certain point, I had the problem that one of the signals wasn't  
dropped fast enough, which resulted in a weird timing-issue.

In the end, I managed to fix my particular by adding a state with a  
small delay in my FSM, but -looking back- it is probably also possible  
to have done this with some additional checks in the state-machine.



Question: are there known "best practices" when designing a  
handshacking-protocol between different modules in a FPGA design?
Is there documentation about this? Or text-books?


My question is not about this particular bug but a generic question on  
"do-s" and "do not-s" in general.



Kristoff

Re: handshacking between modules, best practices ?
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I like the handhaking done in the various AXI like protocol's from ARM -  
basically "VALID", "READY" signals.  The key to making things work is there's
NO combinational paths between a VALID and a READY port i.e. the protocol is
fully synchronous with all module I/O registered.  

Asynch handshaking is another beast altogether.  I'm assuming you're not
talking about that.

Do a web search on the AXI protocols.  ARM's specific document is titled
"AMBA AXI and ACE Protocol Specification".  The handshaking is described
in section A3.2.1

Regards,

Mark



Re: handshacking between modules, best practices ?
Hi Mark,




On 04-04-17 18:03, Mark Curry wrote:

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(...)
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Thanks for the link. Very interesting reading.

Yes, the handshaking protocol I used was syncronised, but I only used  
the positive edge of the clock.

The AXI protocol used the positive edge of the clock to set the  
control-signals and the negative edge of the clock to clear them.

That's indeed a good idea. I'll try to use this in my handshaking  
mechanism to try to make it more robust.


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Kristoff


Re: handshacking between modules, best practices ?
On 4/4/2017 3:36 PM, kristoff wrote:
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Looking at section A3.2 I don't see any signals changing state on the  
falling edge of the clock.  Where do you see this?  It is *very* hard to  
design synchronous logic that operates on both edges of the clock.  The  
two sides of an interface can operate on different clock edges, but this  
only gives half a clock cycle for timing.

Am I completely missing something?

--  

Rick C

Re: handshacking between modules, best practices ?
On 04/04/2017 12:36 PM, kristoff wrote:
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NO NO NO STOP STOP STOP.

The AXI handshake protocols DO NOT do that.  They are, like all good  
synchronous logic should be, sensitive only to the rising edge of the clock.

What the AXI handshake protocol does is use the concept of "mutually  
agreed upon".  If at the rising clock edge a) the master has already  
asserted VALID and b) the slave has already asserted READY, then the  
information present on all the rest of the wires is agreed to have been  
handed off from the master to the slave.  Otherwise, that information  
(if available) is still the master's responsibility.

The point is that there's no need for a recovery cycle.  The master can  
leave VALID asserted and change to new valid data.  The slave can leave  
READY asserted if it doesn't need to wait while it processes the data  
that it just picked up, and the next information can be transferred on  
the very next rising edge.  But this comes with the requirement that  
whether the master's data is valid is entirely uninformed by whether the  
slave is ready for it and vice versa.

--  
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Re: handshacking between modules, best practices ?
On 4/4/2017 11:08 AM, kristoff wrote:
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I've not used handshakes very often.  What would be going on that a  
handshake is required?  Are you talking about clock domain crossing?  Or  
are you talking about two FSMs talking to each other.  In both cases I  
use a direct handshake where one signal does not change state until the  
other "sees" it and acknowledges the previous change.

0,0 -> 1,0 -> 1,1 -> 0,1 -> 0,0

This has no opportunity for a race or timing problem.  Is there  
something I am missing?

--  

Rick C

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