Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...

Hi, I would like to pose an interesting guess topics for experienced engineers: What is the largest number of state machines in a current chip design:

1k, 10k or ...

I have finished 8 projects and only counted 27 state machines in one of my biggest designs.

I may know the answer. The final result may surprise everyone who gives a guess.

Weng

Reply to
Weng Tianxiang
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I am afraid as it stands your question does not make any sense.

These state machines:

  1. How many states does each has?
  2. State encoding, any associated datapath, operation?

BTW 27 is not a small number but the quality of your work questionable. Maybe you could live with a smaller number of FSMs. I just say that 27 doesn't say anything. 42 either ^_^

Nikolaos Kavvadias

Reply to
Uncle Noah

Hi NK, The guess is about what the largest number of state machine a current chip may contain is.

It doesn't ask how many states each state machine has or what coding method is used.

Just guess the largest number of state machine in a current chip design.

It is not an easy guess, because your experiences may fall short of imagination.

Why I listed 27 state machines is I used to make a wrong guessing about the number, only based on my experiences with digital designs. I guess most of experienced engineers may have the same experiences as I had.

Weng

Reply to
Weng Tianxiang
27 is far too little. I reckon its more like a billion state machines, or perhaps a bit more these days. Asics and FPGAS(?) can have more than a billion transistors. A transistor can have at least 2 states (on or off), so I suppose you can say a transistor is a state machine.

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Reply to
Andrew FPGA

The most state machines any design can have is the same as the number of registers available on the design. Each register could be counted as a 2 state FSM. so in todays FPGAs, there are is a maximum of somewhere in the hundreds of thousands of FSMs.

Reply to
Tricky

IF OP = "Weng Tianxiang" AND group = comp_arch_fpga THEN be_prepared_for_a_long_thread; ORIF crossposted = to_comp_lang_vhdl THEN this_could_go_on_all_week; ANDIF both_the_above THEN make_that_a_month; BUTIF plonk! THEN blessed_relief; ELSIF experiences < imagination THEN OP_question

Reply to
Symon

Hi, I don't say how many state machines a design CAN or MAY generate, but I say GUESS what the largest number of state machines a real design ACTUALLY HAS GENERATED and those state machines are critical, not trivial in design functions.

The problem core is how you know other people's design internal affairs?

You may not have a chance to generate so many state machines and you may not have the knowledge about why there are so many state machines.

I guess less than 27 engineers in the world who have a chance to do the designs and have the experiences.

All who have responded to the post so far seem to be no knowledge about it and just missed the target.

Weng

Reply to
Weng Tianxiang

As others have said, how do you define a state machine? Is an SRAM bit a state machine? They fit quite a few of them onto a chip these days...

(followups set to remove crosspost)

--
Philip Potter pgp  doc.ic.ac.uk
Reply to
Philip Potter

Hi, OK, a state machine is defined by standard one process or two processes in VHDL.

There is no short cut.

It can be implemented in anywhere in a design and where the state machine is located is decided by compilers and beyond the interest of this topics.

I have to expand the guess to include Verilog group people, because VHDL people may have no chance to do the designs.

I may know the answer. The final result may surprise everyone who gives a guess.

Thank you.

Weng

Reply to
Weng Tianxiang

Ok Weng,

Since you obviously don't understand the questions the people who have responded...

let's define a state machine as a process or processes that have a classic "state variable". Sigh... Furthermore since you rejected the concept that our guess should not be based on what is "possible" but instead on what has actually been done...

I will answer you question that ***I*** have created the design that has the most classic state machines in it. And since you know the answer you will tell ***me** how many I had to use. Hint: It's more than 27 and I know you ***will*** be surprised by the answer!

Shannon

Reply to
Shannon

Hi Shannon, "let's define a state machine as a process or processes that have a classic "state variable". Sigh... "

I don't write code for them, but you can expect how people in VHDL define a state machine: by using type (...) as I like to do, but not necessarily.

I cannot guess the largest number of state machines you have written for a design, but I know clearly the number of state machines you may have written in a design is less than 100k. Any question?

Weng

Reply to
Weng Tianxiang

Hi Glen, There is a theory behind to resolve the problem.

A state machine can be defined in such a scentific way:

  1. All states in a state machine have their own names;
  2. All states in a state machine are mutually exclusive;
  3. Only one state is active in any cycle;
  4. The number of states in a state machine must be 2 or more;
  5. There must have either asynchronous or a synchronous reset signal for the state machine and after their assertion, the state machine must be in initial state.

I guess there are less than 27 engineers in the world who have the experiences to do the designs.

If your experiences are fully in FPGA and VHDL worlds, you may never have a chance to get a right guess with any possible wildest imagination,

Any more question?

Weng

Reply to
Weng Tianxiang

Ok, so we have your mysterious answer then. The most state machines is 100k. Ok.. ho hum. So? Is there a point to this drivel?

Shannon

Reply to
Shannon

This is not an easy question.

I could say that every flip-flop is a state machine, in which case the number is very large. I could say that the entire system is a state machine, in which case the answer is one.

We partition systems when we design them, and design separate state machines. Others may look at the system differently, and find a different count.

-- glen

Reply to
glen herrmannsfeldt

[snip]

What are you smoking? Care to share?

--
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
Reply to
Tobias Weingartner

Hmm. Your definition of a state machine differs from established FSM theory. You focus only on the textual description.

With your definition a CPU-core and its ROM is not a state machine. Also a shift register used to control other logic would not be a state machine. Any script generated state machines also do not count. Self resetting state machine (JTAG controller anyone?) are also no state machines because there is no reset signal.

The definition of a state machine that I am used to is: A set of storage elements that are connected in a way that the following state of the elements depends on the previous state. State machines can be arbitrarily partitionend and merged. The whole chip can be analyzed as one big state machine (usually not a big idea) or each individual flip-flop can be interpreted as a state machine (also often a bad idea).

But to give you the benefit of doubt and return to your orginal question: Smith-Waterman hardware implementations instantiate tens of thousands of identical state machines. Oh, wait, the implentation that we used had not reset. Damn.

Kolja Sulimma

Reply to
comp.arch.fpga

(snip)

Like the ones that Paracel used to build and sell as real systems?

Which one was that?

-- glen

Reply to
glen herrmannsfeldt

Far too restrictive. In a TDMA architecture I implemented, one RAM contains

512 locations of N bits each: 512 individual state machines. Each 'virtual process' was identical, but had different inputs. For this particular design, a lower bound on the number of states would be 4*512 = 2048, since I had four instances of that particular module. Probably double that, due to similar logic structures downstream. If it were appropriate for the application, scale it up appropriately.

Depending on required processing speed, state machine complexity, target device capabilities, etc., an internal (or external) RAM could contain thousands -- or millions -- of individal state machines.

For my particular case, the next states were defined by equations, the last states were the outputs of the RAMs, and the particular state machine was selected by the RAMs address. (I instantiated the RAMs, but they could have been generated by a process. However, the tools aren't always that good at properly inferring dual-port RAMs, so if you need a particular structure... )

So, what are the limiting factors? Available logic, available storage (registers and memory), creativity, and objectives.

What is the value of the answer?

JTW

Reply to
jtw

ROFL, how could I have missed this posting for 3 days... LOL

Thomas

Reply to
Thomas Entner

Hi JTW, Your response is suggestive and I would like to see your coding to determine if they are state machines.

I don't exclude RAM used as state machines.

If you can do it, it is better. Xilinx has an application note devoted to the BRAM used as state machine and I read the note carefully. But I never use their ideas to use BRAM . I don't have any idea to use the BRAM as a tool for 10k state machines.

There are 10 millions bits of BRAM, you must also have a legitimate reason to use so many state machines in a design. There is seldom a design in FPGA world that would need 100k state machines for a reason.

My answer to my quiz is much larger than 100k state machines in a finished design that is open to use for any one in the topic groups.

Weng

Reply to
Weng Tianxiang

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