Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc

"Symon" schrieb im Newsbeitrag news:42a72697 snipped-for-privacy@x-privat.org...

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OK, 99% agreed. The cutting edge parts shall have cutting edge speed. An no one will argue about Virtex-4 beeing not cutting edge, right?

;-)

dispute

said,

We can make it, IGOR. Charge me another megavolt. HE IS ALIVE!!! There can be only one Frankenstein. ;-)

Regards Falk

What if a bank has to be shared? Does it help to have an unused buffer zone of pins between clock domains? Does it help to have (hard) ground pins between domains?

And just how much does putting different domains into different banks buy in the way of reduced susceptibility? I've been doing that for years, but I have no hard data to tell me what I'm buying, if anything.

Is it better to cut the power plane into separate mini-Vccos, or have a single, low-impedance Vcco plane? (I'm guessing on the latter for all but quasi-analog stuff, such as Vccaux for the DCMs.)

At any rate, these are the kinds of questions I'd like to see the vendors tackle, preferably backed up by some lab work.

By the way, I've been looking through one of the Xilinx V4 demo board schematics, and it turns out the designers created pseudo-differential I/O signals (i.e., differential signals, one side of which goes only to a termination) in an attempt to lower SSO. I recall hearing that such a thing wouldn't work with Xilinx chips. Guess the story changes from day to day.

Take care, Bob Perlman Cambrian Design Works

Where the effects are common-mode inductance, and even cap-crosstalk, this grouping all helps.

As Peter A. has said, it is the cross-domain noise that has the potential for inflicting most damage.

-jg

Hi Symon,

Don't I know it... Actually, it's easy to deduct the length of the trace from the ringing frequency.

I even ran in to this in 1994 when we had a 16MHz design and used a few

74HCT244 buffers on a bus. We could in the end only get the design working by replacing the buffers with 74LS244s because of all the noise the high slew rate was causing.

So no, this is not an FPGA-only problem.

Best regards,

Ben

Bob,

Great thread. See below for my comments,

Aust> Symon -

Yes, isolation is a good thing. More unused pins between domains is also a good thing, as there are more ground/Vcco pairs for return currents.

But, it is true that adding all the grounds in the world don't help after the first set are added. Maxwell's equations show that return currents always flow next to the source conductor, so adding conductors around the existing return conductor offer little or no benefit, unless the return currents are split between return paths, taking advantage of the extra returns.

BART (the rapid transit system of the SF Bay Area) illustrates the common misconception: the third rail is close to one side of the track. 1000V DC: The engineer said that when a train is on the train section, return current is split equally from the supply rail through the train motors back to the returns exactly by 1/2 and 1/2.

Wrong. Maxwell's equations (for DC) show that the return current is based on fields, which is based on geometry, so the return current is

2/3 in the closest rail, and 1/3 in the far rail.

Just because the engineer said so, did not make reality change, and as a result when the first train location system was activated it showed that there was a train in every section where there was not a train, and no train in the sections that had trains in them (true story). The traffic control center freaked out.

The problem could have been solved easily with programmable logic (just invert), but alas, there was no programmable logic in those days.

Back to the topic at hand -

Virtual grounds are almost useless in the new V4 SparseChevron package, as the grounding is so good, using an IO as a poor man's ground is of little to no benefit.

To cut, or not to cut? That is the dilemna. A cut up plane will have much less good high quality capacitance (which is good for byapssing above 100 MHz where bypass caps are almost worthless). But, sometimes you are layer limited, and you just have to do it (cut things up).

If you work with one of our FAE SI experts, we can show you the effectiveness of pcb interplane capacitance on bypassing, and then it is just a question of how good do you really want your bypassing solution to be?

More solid planes, results in fewer, or less exotic caps. For example, the X2Y caps (look like a standard surface mount cap with two center electrodes) has remarkably lower self inductance/ESR, and can go a long way to improving the bypassing solution at the expense of ... expense. But often fewer caps are needed, and you can use the split planes as a result. My group (the FPGA Lab) is happy to talk to your FAE and help them with extreme design solutions (where things get tough, and compromises have to be made).

Just because we have folks who like to experiment doesn't mean we endorse something, or that it works. They are (were) trying to find ways to improve things. Pseudo-differential has a lot of reasons why it doesn't work, which start with the fact that they are single ended, and the load is not balanced at all. Imagine there is 0.5 pF mis-match between the two IO's: that immediately leads to significant common currents at the edge rates. It turns out if you force the differential balance, you can make such an arrangement better, but it will still be inferior to a real balanced differential driver (like LVDS, or CML of the MGTs). One also has to look at the mismatch in time of two single ended IOs (they are not switcing at the same time like a differential IO), as well as the mismatch at the receiver end: is the receiver perfectly differential balanced? Do the two received waveforms overlap in time 100%? Only "real" LVDS pairs are routed in the package with flight time matching (it is part of the LVDS specification).

Hi Symon,

This is a software setting. Altera for some reason insists on 'standard' slew rates being the fastest, and has had a 'Slow Slew rate' setting ever since the Flex10K. This 'Slow Slew Rate' setting can be set on a per-pin basis and pretty much limits your I/O switching frequency to ~750MHz, but then again, I wouldn't want to use a single-ended standard higher than

350-400MHz anyway unless I had some serious simulation software, a few weeks to spare to get the layout right, and a large supply of aspirin. With differential standards there's no need to turn on the slew rate limiter, so LVDS and other protocols don't cause problems.

Also, the power/ground concentration in the center allows for less headaches when minimizing the number of PCB layers - you can pretty much forget about the inner few rows because they'll be power and ground anyway.

Best regards,

Ben