Graphical VHDL Viewer ?

Hi St=E9phane,

You can use ISE (or not!) from Xilinx, since release 8 you have the possibility to show the schematic equivalent of your hdl, try right mouse button over 'design tools' or similar, after synthesis using XST, then you can browse into the blocks, and so on. I guess that using symplify or other tools you have something equivalent.

good luck

csb

uce

Hi,

Thanks for your answer.

I saw the RTL viewer but you have to synthesis your design. My goal is to view a simple level of design without providing the source file of each sub component. Which can be quite long for complexe designs.

Stéphane.

"csantos" a écrit dans le message de news: snipped-for-privacy@q5g2000prf.googlegroups.com... Hi Stéphane,

You can use ISE (or not!) from Xilinx, since release 8 you have the possibility to show the schematic equivalent of your hdl, try right mouse button over 'design tools' or similar, after synthesis using XST, then you can browse into the blocks, and so on. I guess that using symplify or other tools you have something equivalent.

good luck

csb

I use the quartus rtl viewer. example:

If I synthesize a structural entity with null architectures, I get just the top level block diagram.

-- Mike Treseler

uce

There are Advanced Dataflow Viewer in Aldec Active-HDL and Dataflow Viewer in ModelSim. But they are not free. They are both pretty similar, after compiling the design you can browse its graphical representation consisting of architectures, processes, ports and connections. You can also use Dataflow Viewer for debugging during simulation.

Advanced Dataflow demo from Aldec:

uce

you can try FPGA Advantage, it's mentor product. I use this for develop for years and it's very easy for generate graphic VHDL.

doxygen?

Hi,

There is a simple solution, just use the 'black_box' constraint applied to your top lovel blocks, you can synthetize without needing to provide the code of the components, this will create a schematic of the top level, does it help?

csb

hdl

uce

I'd like to mention Lattice HDL Explorer. As far as I understand it's exactly the thing you're looking for. It's not exactly free, it's part of Lattice tool ispLever. The tools aren't too expensive and also you'll be able to get a 60 days free evaluation if you'd like, just contact Lattice local person for this.

Hope this helps, Alex Y.

uce

It will not help in your current situation, but I would recommend Active-HDL for your future designs (not free unfortunately). What we do is that we do the design in a graphical manner with boxes connected to each other in a schematic editor. Then each box is a VHDL file or another level of schematic. That way it us MUCH easier to understand the design than to try to understand the VHDL netlist. Each schematic is converted automatically to a VHDL file, so it's always possible to go back to a simple VHDL netlist if desired.

Patrick