Gnd plane coupling with DDR routing from FPGA <-> DDR?

Hopefully some of you guys who have gone through this can comment...

We're doing our first board with a couple of DDRs and have a query with ground plane coupling when routing the signals out of the FPGA.

We're hoping to get away with a 6 layer board so the stack is..

sig1 GND sig2 sig3 PWR sig4

Any signals that're routed from the FPBA ball to sig4 won't have the same good GND return paths to the FPGA that those coming out on sig1/sig2 will have.

We're aiming to run the interface at ~2* 120MHz.

We don't have any simulation tools so are having to design using best practice.

We can place a GND island in on the PWR layer under the FPGA/DDR with plenty of vias stitching it up to the 'real' GND plane, but this will make the PWR routing more difficult.

Does this matter, will the difference in GND coupling be a problem?

Some of the app notes we've read suggest that the track impedance isn't too much of a problem.

Thanks for any pointers,

Nial

Reply to
Nial Stewart
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I haven't yet, but I'm asking myself the same sort of questions for the same sort of reasons.

Just an opinion.

While the board may be routable on 6 layers ...

check the incremental cost of 8 layers over 6. Sometimes it's 10% or less.

That gives you a second ground plane and allows you to improve power distribution.

Unless this is a HIGHLY cost-sensitive product, that looks like a good investment to me, given the cost of the time involved in engineering a solution any more closely.

- Brian

Reply to
Brian Drummond

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

I would never split a plane except as a last resort (unless you can sandwich it between two solid planes - I often use a four layer GND, split power, split power, GND sandwich in the middle of 16-20 layer boards), because of the issues with traces crossing the split. If you must stick to six layers then you need to make the power plane look like a ground plane by ensuring that there are adequate decoupling capacitors spread uniformly across the board, such that no point on the board is more than some short distance from a capacitor. The AC return current can flow along the power plane and through the capacitor to ground. Of course, you want to reduce the inductance so use 0402 or 0603 parts with vias very close to the pads.

Reply to
David Spencer

I have designed a similar 4 layer board which runs DDR at 100MHz. As long as the traces between the FPGA and the DDR memory do not cross plane borders, you'll probably be fine. In my design I optimized the connections so I did have at most one via close to the FPGA pin in traces between the FPGA and DDR.

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Reply to
Nico Coesel

Power and ground are not going to be forming a very good capacitor to supply power so you're making a big compromise right there, it won't be a really low inductance pathway to deliver power to the parts on the board. Ideally you'd like to have two more layers, move PWR up to be underneath GND and then mirror that on the bottom side (i.e. sig1, GND, PWR, sig2, sig3, PWR, GND, sig4). Whether your 6 layer bites you or not will depend entirely on how much switching is going on and how demanding the parts are. I recently consulted on a design that had the above type of stackup and the PCB was unable to deliver enough

3.3V to the FPGA and would cause it to functionally upset, the board failed. Adding the planes and putting power adjacent to ground was the biggest impact in the fix, other remedies that were tried to band aid the boards while waiting for the improved stackup design had only marginal impact.

As long as you're not talking about signals having to cross a break in the power plane itself, being adjacent to the cut up power plane is not much different. It all comes down to how much copper is on that plane adjacent to the signal. The electromagnetic field does not care the voltage level on the hunk of metal that it runs into first.

Is that 2 DDRs at 120 MHz? Or 240 MHz?

If you can't spring for si tools, then I'd suggest the following resources that you should peruse in besides just this particular newsgroup

  1. "Right the First Time: A Practical Handbook on High Speed PCB Design and System Design". Volumes 1 and 2, by Lee W. Ritchey. Each will set you back about USD I think but they are both well worth it. Can be purchased from speedingedge.com (I have no financial or other interest in the book or the Speeding Edge company, this is just a recommendation for what I've found to be an excellent resource).
  2. formatting link
    which is a newsgroup dedicated to signal integrity issues. Post your questions up there and you'll get well informed responses from a number of experts. comp.arch.fpga contains some people that know what they're talking about and others that only think they know. In fairness though, this FPGA newsgroup has a different focus that handles issues that run through the whole spectrum of issues related to FPGA design starting from synthesis/simulation tool problems, coding formats, downloading, component packaging and PCB design, etc.

Putting the island in won't help at all.

Kevin Jennings

Reply to
KJ

"Nial Stewart" wrote in message news: snipped-for-privacy@mid.individual.net...

Hi Nial,

Wow, you got some strange answers! (IMHO, natch.) The same old chestnuts about PWR and GND planes being used as bypass capacitance. Waste of time. The tiny capacitance is no use to you as you have to attach the FPGA to it _VIA_ inductance. This is why FPGA companies embed bypass caps in the package. BTW, what PWR is on the plane? VCCO for your DDR bank? VCCINT?

Also, 16-20 layer boards? I guess it'll work, but I'm glad I'm not paying for it.

Good answers you got are, 'use two more layers', 'simulate', 'SI-LIST', and 'use as few vias as possible'. Oh, and don't cross gaps in planes, but we all know that, right?

I'd do something like this:-

sig gnd sig sig gnd sig

I'd route the powers on one or two of the internal layers. I'd use copper pours and/or little puddles of cu for each supply. I'd use X2Y caps backside of the FPGA for bypassing. (Google X2Y FPGA) If a fast signal changes its ground reference from one ground plane to another, I'd put a GND via nearby. Several fast signals can share a single ground via.

Austin's right, if you're a beginner you should certainly use a simulator. Maybe you can borrow one from somewhere? Any universities nearby? However, the 'two ground planes' design makes it considerably harder to get it wrong, especially at 120MHz.

HTH. Syms.

p.s. You did search back through CAF for previous threads, right? ;-)

Reply to
Symon

I disagree, as does most of the research done into the subject. The use of buried capacitance, typically by having adjacent power and ground planes separated by as small a distance as possible (2 thou is normal), has been shown to be very favorable when compared to discrete decoupling caps because although the capacitance is much lower the inductance is very much lower so the overall impedence is significantly lower. There is an article about it here:

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The requirement for discrete capacitors on the BGA substrate itself is a different matter. That is to compensate for the inductance of the BGA ball and tracking and is necessary regardless of how the board level decoupling is implemented.

Reply to
David Spencer

I've had good results with : sig1 sig2 GND PWR sig3 sig4

If you really need to, you can make the traces on sig1 and sig4 a little wider to keep the impedance near the right value. Keeping GND and PWR planes close together helps. If sig1 and sig2 are orthogonal, and same for sig3 and sig4, there should be minimal crosstalk. I have not done a DDR memory, but signal integrity is signal integrity.

Jon

Reply to
Jon Elson

I understand that as 120 MHz clock, 240 MHz data rate during bursts. Recently I had a similar case - processor (not FPGA), which is in a 256 ball FPGA, 133 MHz clock/266 MHz data burst rate. However, I was much more conservatiive with my stackup. Instead of your

I did 6 layers as well, but my stackup is:

signal GND PWR PWR GND signal

Worked the first time, actually see the prototype (very first one assembled, design for an external customer) board here:

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.

The two DDRAMs (x16 each) are close to the board centre, easy to spot.

Here is the bare board in some better detail:

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.

The board is routed at 6 mil most of the time which goes down to somewhat over 4 mil for the worst case angular ring and for traces between BGA pads (3 traces between a pair of 1.27mm spaced pads/vias. Have used these rules on other boards as well, have never failed me. Routing takes somewhat more head scratching (or is it hear teraing... :-) ), but has always been doable. Now what do I do with a 0.8mm BGA (soon to be routed here, never done so far) is yet to be seen... :-)

At these low speeds, buying signal integrity tools/consultants will be a sheer waste. You need neither (although ask that on the SI list and you will be overwhelmed by suggestions to buy all things imaginable... make sure to ignore such advice, the SI tool writers and SI consultants are pretty active on that list). Buy a tool by the usual criterion, that is, only if you know exactly what you want the tool to do for you and if you understand how it will do it. Buying a software blindly expecting it to solve your problems will typically result in more, not less problems. Which does not mean most people nowadays are not doing exactly that, of course :-).

Again, 120 MHz is nearly DC nowadays. You don't need any fancy SI tools to do it.

Dimiter

------------------------------------------------------ Dimiter Popoff Transgalactic Instruments

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Reply to
Didi

Sorry for the typos above, it should read "or is it hair tear> > We're aiming to run the interface at ~2* 120MHz.

Reply to
Didi

As Jon suggests, putting power and ground adjacent is generally a bit better.

But either stackup will work fine. As long as the power plane (or its split pours) is pretty well bypassed to ground, the signals can't tell the difference between them or ground as the "return" plane. If power and ground are adjacent layers, the increased plane-plane capacitance keeps them a bit more equipotential at very high frequencies.

Don't worry about signals crossing small slits on a split power plane; that is simply not an issue in real life. You can barely resolve crossings like that on a 20 GHz TDR... it's down in the wiggles caused by the fiberglass weave.

We've done pretty hairy stuff with Xilinx bga's on 6 layers, with no signal integrity problems.

The thing to watch out for is signal-signal crosstalk, especially on clock lines. Clocks need especially serious signal integrity treatment these days. And "clocks" includes CCLK!

I suppose I could post some layer pics...

John

Reply to
John Larkin

Nial

I would expect from our experience that the DDR could be routed in 3 layers assuming you are attaching to a FPGA and a sensible pinout is chosen. Our product Tarfessock1 achieves the connection of a DDR2 chip in principally 2 layers with a couple of straggler signals on a 3rd layer. If this product was a less compoonent dense product we certainly would do it all in the 2 layers.

Taking that as a starting point you could use one of your tracking layers as a localised ground layer using a polygon fill and you can have a fairly good electrical setup for high speed signals. We use some of the recomendations in Xilinx XAPP693 for layer structure and never had an issue.We don't use all the recomendations of this applications note as they are impractical to achieve on a cost sensitive board.

Signal integrity tools are a nice toy but they are only as good as the information fed into them. There are generally also expensive although you can argue that against the cost of a failed board. Even if you know your pcb manufacturer at this point, and the materials they use specifically, then at best things like the dielectric constants and layer spacing vary a lot over product batches unless you pay a lot to get boards made to an exact specification and get them tested with resultant yield drop and cost implications. I doubt that any PC motherboard manufactures ever do that and they make an awful lot of boards. Those boards also tend to be 4 layers or sometimes 6 layers.

John Adair Enterpo> Hopefully some of you guys who have gone through this can

Reply to
John Adair

buried capacitance,

distance as possible

discrete decoupling caps

lower so the overall

David,

I too am skeptical about the amount of decoupling that close GND/PWR plane coupling can provice.

In that atricle above they quote 560pF/sq inch. Most BGAs are smaller than that.

The article suggests that this sort of capacitance is useful for 'random' logic where there's little synchronisation between gates drawing power.

We're using FPGAs that tend to be largely synchronous.

Page 24 says...

to

?

I think I'll rely on my decouplers, the X2Y devices Symon pointed out (again) seem useful.

Nial.

Reply to
Nial Stewart

Hi Symon,

I was hoping you'd stick your oar in!

it.

Indeed, this is self funded so I'd like ot keep costs down where possible (with the proviso things should work).

8 Layers is the brute force answer to the problem. It should definitely work, but it would be good to find a more elegant solution to the problem.

cross gaps in planes,

To use a Belfast expression

"Do you think I came up the Lagan in a bubble?".

No (adjacent) plane splits will be crossed.

pours and/or little

I think you've said before that you've got away with routing power in like this with no problems.

They look good, and as they're available from Digikey they might be a goer.

The downside is that we're currently using 0402's with round pads on the back of the board so they fit neatly just at the PWR/GND pins.

The X2Ys would have to be round the edges, but it could be worth adding a few in.

another, I'd put a GND via

The idea was to create a localised GND plane on the PWR layer with vias to the 'real' GND layer and a matching linking via beside any point at which a trace goes from the bottom layer to top layer.

Maybe you can borrow

design makes it

But as others have said, 120MHz is almost DC these days!

Oh aye, there wasn't too much about routing to DDRs specifically but as usual all advice was conflicting as here!

:-)

Thansk,

Nial.

Reply to
Nial Stewart

it between two solid

in the middle of

As you say below signals can use the PWR plane as a 'pseudo gnd'.

By using this stack are you not loosing the ability to route two internal signal layers adjacent to the GND planes, and the additional use of the PWR planes as pseudo grounds?

like a ground plane by

the board, such

The AC return

course, you want to

pads.

That's a thought. The bank of the FPGA driving the DDR and the device itself are on the same unbroken power plane. There's also plenty of decoupling round both devices so we might be OK.

Nial.

Reply to
Nial Stewart

Are you not missing out on one layer closely coupling to the GND and using the PWR as a pseudo GND like this?

to keep the

helps. If sig1 and

Indeed.

Nial.

Reply to
Nial Stewart

That's not very routing efficient.

Thanks for this info.

We've been working from a Micron app note which suggests 8 mil min clearances between data lines.

On the other hand this is a short point to point connection so we can probably get away with a lot more than others with more onerous topologies.

Thanks for an alternative viewpoint.

Hopefully.

Nial.

Reply to
Nial Stewart

As below, I'm not convinced this is a problem.

Good _enough_ supply paths with sufficient local decoupling should do?

Might it not have been due to bad signal return path integrity or insufficient grounding?

(I'm not arguing here, just posing the question).

Alan (if you're reading this), guess what you're getting for Christmas!

Thanks for the pointers Kevin,

Nial.

Reply to
Nial Stewart

We've been following one of the Micron app notes here, especially wrt the clocks. It's a fairly short pt to pt connection so hopefully we should be OK.

Thanks,

Nial.

Reply to
Nial Stewart

I'm not doing the routing but I think it'll all come out on 3 layers. We have a few spare pins in the banks we're using so should be able to shuffle things about.

We'll have a look at that, although I think we've been overly paranoid. Top and layer 3 are tightly coupled to the GND plane, the bottom layer should be coupled to the PWR plane if we make sure it's sufficiently decoupled (as elsewhere in the thread).

Aye, but they are purveyors of magic!

Looking at the complexity/density/performance of a typical PC motherboard I'm still impressed at the price they knock them out for.

Thanks John.

Nial.

Reply to
Nial Stewart

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